Steve Knapp wrote:> > The BGA packages have superior signal integrity. >Well, the existing VQ100's aren't all that horrible; and if you can make this or the next generation available in a ground paddle QFP or QFN, the VQ100 size packages might even be better than the CP132's. Toss in 2.5V-or-less I/O banks with better performance, and there'll be chocolate cake all 'round.> > The different SSO numbers on the quad-flat packages are > purposely lower due to their merely average signal integrity. >Well, those mysterious "fours" seem to have reappeared across the board again for the S3E differential drivers in VQ/PQ packages, with the spiffy well-balanced current mode drivers once again inconsistently assigned the same limit as have the older voltage mode, psuedo-differential, CMOS-with-resistors BLVDS outputs. Those mystery fours also do not show the expected improvement in the smaller VQ package as do both the single ended standards and the latest Spartan-3 SSO limits for their current mode differential drivers. In Spartan-3, the datasheet differential SSO's underwent the following series of gyrations: - DS099-3 (v1.1) July 11, 2003 - no SSO lmits in datasheet - DS099-3 (v1.3) March 4, 2004 - blank SSO table column for PQ/VQ packages - blank SSO for all differential standards, PQ/VQ/BGA - DS099-3 (v1.4) August 24, 2004 - deleted SSO table column for VQ/PQ packages - all differential drivers, of any type, in BGA, have a listed SSO limit of 4 - LVDS_25_DCI input SSO limit of 4 in BGA - DS099-3 (v1.5) December 17, 2004 - reappearance of VQ/PQ packages, with mysterious 4's across the board for the balanced current mode drivers for VQ/PQ/BGA - VQ/PQ limit of 1 or 2 for BLVDS/PECL - LVDS_25_DCI input SSO limit of 4 - DS099-3 (v1.6) August 19, 2005 - has more reasonable numbers for some of the current mode drivers, with better numbers for the smallest package as would be expected - VQ/PQ limit of 1 or 2 for BLVDS/PECL - LVDS_25_DCI input SSO limits have vanished - DS099-3 (v2.0) April 3, 2006 - and even as we speak, your latest S3 datasheet has again improved the current mode driver SSO limits for the ones formerly stuck at '4'> >Also, SSOs are only for outputs. You can have as many LVDS inputs >that will fit in an I/O bank. >For S3, Austin Lesea has indicated [2] that the LVDS_25_DCI numbers in the S3 datasheet SSO tables were there to handle the DCI terminator current; however, those DCI "fours" were removed in later SSO tables. I'd avoid using many parallel DCI inputs in the same VQ/PQ bank [1,3] without first having some measurements of the internal DCI startup VCCO rail collapse. Thankfully, S3E now has those approximately 120 ohm DT terminations. Brian [1] http://groups.google.com/group/comp.arch.fpga/msg/1ddb0bd333382d06 [2] http://groups.google.com/group/comp.arch.fpga/msg/52a0a4a0dbe79ebe [3] http://groups.google.com/group/comp.arch.fpga/msg/428d53c767e64c9a
LVDS in Cyclone-II
Started by ●April 5, 2006
Reply by ●April 7, 20062006-04-07
Reply by ●April 7, 20062006-04-07
"Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> wrote in message news:1144366043.186825.39990@e56g2000cwe.googlegroups.com...> John_H wrote:<snip>>> Oops.>> I just remembered - there are only 4 banks on the Spartan3E. Yikes! >> The pairs per bank are 1.4x-2x the Spartan3 values so it looks like they >> may be legit.>> I sure hope those SSOs get changed!!!> Which package did you plan to use and how many LVDS output pairs are > required? The different SSO numbers on the quad-flat packages are > purposely lower due to their merely average signal integrity. The BGA > packages have superior signal integrity. > > Here's how you would calculate the recommended limit using the data > sheet values. > http://www.xilinx.com/bvdocs/publications/ds312.pdf > > Let's assume that you're using the TQ144 package, which has the > equivalent of 2 VCC/GND pairs per bank (Table 92, page 133). Then, go > to the LVDS_25 section in Table 93 (on page 134), indicating that you > can have 4 LVDS _output pairs_ (emphasis included) per power ground > pair. Multiply the values together to arrive at 8 LVDS _output pairs_ > on a bank in the TQ144 package. Again, the SSOs are a recommendation, > but let's keep it to 8 pairs, which equations to 16 I/O pins. There > are only ~23 I/O on a package edge in the TQ144. The Input-only pins > are not available as outputs. Also, SSOs are only for outputs. You > can have as many LVDS inputs that will fit in an I/O bank.<signature snip> Thanks for the info, Steve. The only time I've had real troubles in the past was getting a feel-good for the improperly specified number of PCI signals per bank for the PQFP. The data sheet does a good job of presenting the SSO information (which isn't seen so clearly in competitors' literature). For my current design I was looking at an LVDS translator on the front end implemented in a separate FPGA. The VQ or TQ package would make sense for such a low pin count application - 4 pairs in, 11 pairs out - but the SSO limits would exclude a simple flow-through design. In the VQ or TQ package I couldn't put all 11 balanced-current LVDS drivers on one bank. The design will end up using Xilinx after all and a BGA package for the front end and the main functionality removes most of the limits. PCI interfaces are something we've implemented a bunch in the past. The SSO numbers for the Spartan3E in the wireframe packages spread the interface out over at least 3 banks if those SSOs are to be believed. That's a bit more of a restriction than I'd expect but they are just wireframe packages. I'm hoping we're at the point soon where the price for wireframes aren't as attractive when compared to the "better" packaging. - John_H
Reply by ●April 7, 20062006-04-07
Brian Davis wrote: [ ... snip ...]> > > Well, those mysterious "fours" seem to have reappeared across > the board again for the S3E differential drivers in VQ/PQ packages, > with the spiffy well-balanced current mode drivers once again > inconsistently assigned the same limit as have the older voltage > mode, psuedo-differential, CMOS-with-resistors BLVDS outputs. > > Those mystery fours also do not show the expected improvement in the > smaller VQ package as do both the single ended standards and the latest > Spartan-3 SSO limits for their current mode differential drivers.The current Spartan-3E data sheet does indeed show those mysterious "fours". We're in the process of updating the Spartan-3E numbers and I expect the mysterious 4's to improve to 6's in the next data sheet release for LVDS, RSDS, and miniLVDS I/O standards. Effectively, this means that you can practically use all available I/O on a bank for LVDS, RSDS, or miniLVDS outputs (okay, you miss one or two pins on the PQ208). The Spartan-3 SSO confusion that you mentioned happened due to the methodology we used at the time. Previously, the SSO numbers were generated strictly from simulation models, which always suffered from huge, conservative guardbands on new processes. Spartan-3 was one of the first commercially available 90 nm devices. The Spartan-3 SSO numbers started out very low and improved once we were able to back up the numbers with real silicon. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.
Reply by ●April 10, 20062006-04-10
