How do I use the DDS core in a verilog flow?

xilinx_user wrote:
> Sir,
> 
> Your comment: "but if you don't want to listen ... ;) " is not helpful.
> I originally had the .v file in  the directory and it did not work.
> Aurelian Lazarut, who is a System Verification Engineer
> for Xilinx Ireland said to remove them and make sure all the edif files
> are in the working directory. As he works for Xilinx I am inclined to
> take his word.
> 
> Just for the record, the comment in the .v file is: "This file cannot
> be synthesized and should only be used with supported simulation
> tools."
> 
> I am sorry you take offense but I am losing time in getting the answer
> I need.
> 
Here is the recipe that always works for me:
I use the ISE GUI. When I have a CoreGen model instantiated in my 
Verilog, ISE leaves a place for the .xco file. In your example, your 
core is called sine_new, so there will be a sine_new.xco. Add that 
source to your project.

Among other files, CoreGen will generate sine_new.edn and sine_new.v . 
You should place these files in same directory as your *.ise file (the 
ISE project file). In general, you can't go wrong if you put every file 
that CoreGen creates into the directory that has your *.ise file.

---
Joe Samson
Pixel Velocity

I think Lasse is right here, the *.v file will act like a "blackbox 
placeholder" (or at least it should)
I have to admit that the message in the header is misleading that this 
file will be used for simulation only, hence the confusion.
however the "normal" flow will be to keep the *.xco file attached to the 
design tree, so Joe's suggestion will hold here.

Aurash

Joseph Samson wrote:

> xilinx_user wrote:
>
>> Sir,
>>
>> Your comment: "but if you don't want to listen ... ;) " is not helpful.
>> I originally had the .v file in  the directory and it did not work.
>> Aurelian Lazarut, who is a System Verification Engineer
>> for Xilinx Ireland said to remove them and make sure all the edif files
>> are in the working directory. As he works for Xilinx I am inclined to
>> take his word.
>>
>> Just for the record, the comment in the .v file is: "This file cannot
>> be synthesized and should only be used with supported simulation
>> tools."
>>
>> I am sorry you take offense but I am losing time in getting the answer
>> I need.
>>
> Here is the recipe that always works for me:
> I use the ISE GUI. When I have a CoreGen model instantiated in my 
> Verilog, ISE leaves a place for the .xco file. In your example, your 
> core is called sine_new, so there will be a sine_new.xco. Add that 
> source to your project.
>
> Among other files, CoreGen will generate sine_new.edn and sine_new.v . 
> You should place these files in same directory as your *.ise file (the 
> ISE project file). In general, you can't go wrong if you put every 
> file that CoreGen creates into the directory that has your *.ise file.
>
> ---
> Joe Samson
> Pixel Velocity



-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Joseph Samson wrote:
> Here is the recipe that always works for me:
> I use the ISE GUI. When I have a CoreGen model instantiated in my
> Verilog, ISE leaves a place for the .xco file. In your example, your
> core is called sine_new, so there will be a sine_new.xco. Add that
> source to your project.
>
> Among other files, CoreGen will generate sine_new.edn and sine_new.v .
> You should place these files in same directory as your *.ise file (the
> ISE project file). In general, you can't go wrong if you put every file
> that CoreGen creates into the directory that has your *.ise file.
>
> ---
> Joe Samson
> Pixel Velocity

Thanks for your posting. Unfortunately I did not check back in time. I
experimented quite a but and discovered the same thing.

I have alot of experience with Verilog/Xilinx, but have not used cores
before. Also, I have not used the Xilinx tools for about 2 years and am
getting re-used to the WEBPACK GUI.

I have another question. I am now trying to simulate the core using the
ISE simulator in Webpack 8.1 I am running into the problem that the
output is always 0 no what frequency I set as the 'quiescent' frequency
for this core.

I know I am doing something wrong. Do you have any general observations
along the lines of your reply to me? Any help with be appreciated.

Best Regards,

Art

xilinx_user wrote:
> 
> I have another question. I am now trying to simulate the core using the
> ISE simulator in Webpack 8.1 I am running into the problem that the
> output is always 0 no what frequency I set as the 'quiescent' frequency
> for this core.
> 
> I know I am doing something wrong. Do you have any general observations
> along the lines of your reply to me? Any help with be appreciated.

In the core generator project options (Project -> Project Options..., 
then Generation tab), you can choose either Behavioral or Structural 
simulation files. Try them both; sometimes one doesn't work. If you do 
this, make sure that you connect the signals correctly when 
instantiating the module. Some cores have the signals in a different 
order depending on whether Behavioral or Structural are chosen.

---
Joe Samson
Pixel Velocity

Joseph Samson wrote:
> xilinx_user wrote:
> >
> > I have another question. I am now trying to simulate the core using the
> > ISE simulator in Webpack 8.1 I am running into the problem that the
> > output is always 0 no what frequency I set as the 'quiescent' frequency
> > for this core.
> >
> > I know I am doing something wrong. Do you have any general observations
> > along the lines of your reply to me? Any help with be appreciated.
>
> In the core generator project options (Project -> Project Options...,
> then Generation tab), you can choose either Behavioral or Structural
> simulation files. Try them both; sometimes one doesn't work. If you do
> this, make sure that you connect the signals correctly when
> instantiating the module. Some cores have the signals in a different
> order depending on whether Behavioral or Structural are chosen.
>
> ---
> Joe Samson
> Pixel Velocity

Thanks. I had already tried both behavioral and structural, and neither
one worked. I then did a post route simulation and that seems to work.

This simulator seems flaky, if not goofy. I am not sure I trust
anything out of it.

In any event, thanks for the help.