High-speed DAC/ADC with FPGA

"rnbrady" <rnbrady@gmail.com> wrote in message
news:1152606377.870160.319660@m73g2000cwd.googlegroups.com...
>
> I'd like to capture and generate signals anywhere from 10kHz to 100MHz.
> It would be great if I could reach 450MHz with some mixing at the front
> end. I don't really need more than 1MHz at a time. So a lower rate with
> a NCO + mixer might be a better bet.

Have you considered undersampling? You could do any part of your band
without needing any mixers and/or excessively high sampling rates. Covering
whole band would require switchable anti-aliasing filters...

/Mikhail

Richard,

just a quick remark : don't forget in your design phase the
bottleneck that can be the ADC-to-CPU interface.
For instance
> ADC08D1500 dual 1500 MSPS, 8 bit ADCs that includes a Xilinx V4 FPGA
> and a USB interface controller on board. The dual converters can be
I understand wouldn't allow to do real time as USB is limited to
480Mbps
if I remember well.

Have a look at this very good article from Xilinx's XCELL magazine
Capturing Data from Gigasample Analog-to-Digital Converters
http://tinyurl.com/ng738
It explains how you can achieve high data rates sampling in an FPGA.

With respect to Signal Integrity then yes, you can achieve 400MSPS
but indeed with a bit of care. Probably the most important things
that you have to check are :
* The length of the traces (clock, data) will have to be equalised
(400MHz is 2.5ns period and 15cm on a PCB is probaply between 1ns
and 1.5ns depending on various parameters).
* as you are going to design the ADC board, I would place series
termination on (the clock, of course) but on the data as well
to make sure there is no ringing on these signals (ie the
resistance is high enough 30 ohms, 40 ohms...).
This is the minimum you have to guarantee on your 2 layer PCB.
Use local power grounds as well.

Hope this helps, 

jb

Richard,

just a quick remark : don't forget in your design phase the
bottleneck that can be the ADC-to-CPU interface.
For instance
> ADC08D1500 dual 1500 MSPS, 8 bit ADCs that includes a Xilinx V4 FPGA
> and a USB interface controller on board. The dual converters can be
I understand wouldn't allow to do real time as USB is limited to
480Mbps
if I remember well.

Have a look at this very good article from Xilinx's XCELL magazine
Capturing Data from Gigasample Analog-to-Digital Converters
http://tinyurl.com/ng738
It explains how you can achieve high data rates sampling in an FPGA.

With respect to Signal Integrity then yes, you can achieve 400MSPS
but indeed with a bit of care. Probably the most important things
that you have to check are :
* The length of the traces (clock, data) will have to be equalised
(400MHz is 2.5ns period and 15cm on a PCB is probaply between 1ns
and 1.5ns depending on various parameters).
* as you are going to design the ADC board, I would place series
termination on (the clock, of course) but on the data as well
to make sure there is no ringing on these signals (ie the
resistance is high enough 30 ohms, 40 ohms...).
This is the minimum you have to guarantee on your 2 layer PCB.
Use local power grounds as well.

Hope this helps,

jb
> Peter Alfke wrote:
> > Many A/D converters have a double-width digital interface, which
> > reduces the FPGA capture rate by a factor two (but doubles the number
> > of bits)
> > I have seen sample rates of 1 Gsps interfaced to FPGAs (guess which
> > ones).
> > Make sure that the sampling clock is as clean as possible. Any jitter
> > will severely impact your analog noise floor, i.e. will reduce the
> > dynamic range.
> >
> > Peter Alfke, Xilinx
> > ====================
> > rnbrady wrote:
> > > Hi folks
> > >
> > > I'm working with an Altera Stratix ep1s10 on a development board. The
> > > data sheet says the IO can operate at rates up to 800 MSPS. If I have a
> > > look on the internet, I see DAC and ADC technology going up to 400
> > > MSPS.
> > >
> > > My application is software defined radio, where the general mantra is
> > > to do as little analog front-end as possible, i.e. sample as fast as
> > > you can.
> > >
> > > What are the limits on my conversion rates? I doubt it's even remotely
> > > possible for me to do data conversion at 400 MSPS? My main concern is
> > > the PCB layout, with about 15cm of track and a header between the FPGA
> > > and the conversion chips. Crosstalk, EMI and impedance matching are all
> > > things I know very little about.
> > >
> > > Is there a more appropraiate group to post on?
> > > 
> > > Thanks in advance,
> > > Richard

The point of the USB interface it not to be able to transfer
sample-rate data in real time, it is presumed that a large amount of
processing (i.e. demodulation, etc.) is done in the fpga to reduce the
output data rate to something that could be handled in real or near
real (buffered) time over the USB interface.

Andy


jean-baptiste.nouvel@jdsu.com wrote:
> Richard,
>
> just a quick remark : don't forget in your design phase the
> bottleneck that can be the ADC-to-CPU interface.
> For instance
> > ADC08D1500 dual 1500 MSPS, 8 bit ADCs that includes a Xilinx V4 FPGA
> > and a USB interface controller on board. The dual converters can be
> I understand wouldn't allow to do real time as USB is limited to
> 480Mbps
> if I remember well.
>
> Have a look at this very good article from Xilinx's XCELL magazine
> Capturing Data from Gigasample Analog-to-Digital Converters
> http://tinyurl.com/ng738
> It explains how you can achieve high data rates sampling in an FPGA.
>
> With respect to Signal Integrity then yes, you can achieve 400MSPS
> but indeed with a bit of care. Probably the most important things
> that you have to check are :
> * The length of the traces (clock, data) will have to be equalised
> (400MHz is 2.5ns period and 15cm on a PCB is probaply between 1ns
> and 1.5ns depending on various parameters).
> * as you are going to design the ADC board, I would place series
> termination on (the clock, of course) but on the data as well
> to make sure there is no ringing on these signals (ie the
> resistance is high enough 30 ohms, 40 ohms...).
> This is the minimum you have to guarantee on your 2 layer PCB.
> Use local power grounds as well.
> 
> Hope this helps, 
> 
> jb

rnbrady wrote:
> Hi guys
>
> Thanks for the helpful replies.
>
>
> > More details are really needed:
> >
> > What type of header are you talking about? I have run signals at 5Gb/s
> > through connectors designed for the task with little loss and very low
> > crosstalk, but they aren't cheap. Is this an existing header?
>
> The headers are existing. They are standard beak-away headers.
>
> > Does this mean you want to run wires, or are you making a circuit board
> > for the A-D? You are unlikely to get high data rates with handwired
> > circuitry (you can get reasonably high speeds, but not too high unless
> > you are an expert in wirewrap and routing ;).
>
> I plan to have a PCB made. We have facilities for two layer PCB
> manufacturing.
>
> > You say you are using a development board. What documentation is there
> > for it? Point us at some details if you have them.
>
> I'm working with an Altera dev kit:
> http://www.altera.com/products/devkits/altera/kit-nios_1S10.html
>
> There is tons of documentaion for the NiosII embedded CPU on this dev
> kit but almost no documnetation on the board itself.
>
> > What is the interface from your A-D converter(s)? Serial? Parallel?
>
> I'd find it simpler to do parallel, there's no shortage of pins.
>
> > Parallel may take more lines, but it also gives the lowest data rate.
> > There are also tricks of synchronised sampling (using multiple
> > converters, suitably calibrated) to increase the effective sample rate,
> > should that be necessary. On that subject, is there a particular A-D
> > device you have in mind, or are you open to suggestions?
>
> Completely open.
>
> > What signal frequency range are you particularly interested in getting?
> > If you are not sure of what to use, this will let others help you
> > choose an appropriate device.
>
> I'd like to capture and generate signals anywhere from 10kHz to 100MHz.
> It would be great if I could reach 450MHz with some mixing at the front
> end. I don't really need more than 1MHz at a time. So a lower rate with
> a NCO + mixer might be a better bet. The basic idea to to be able to
> receice and transmit commercial FM and AM, plus some walkie-talkie FM,
> and maybe some HAM radio, all with as little HW as possible.
>
> >
> > Even if you sample with a decent A-D, you should still (in my opinion)
> > put an anti-aliasing filter on the front end, and buffering to prevent
> > loading. (Some parts have them internally). Unless you have a buffered
> > output from something, you are probably going to have to put down at
> > least some analog circuitry apart from the A-D(s).
>
> This is fine, I simply want to keep it to a minimum.
>
> > Speaking of that, what RF device did you intend to use to get the
> > signal in the first place?
>
> An antenna.
>
> >
> > Answer those (reply to both groups) and some of the denizens of s.e.d.
> > will no doubt dispense some ideas, and no doubt ask more questions.
>
> Thanks again. I really appreciate your input.
>
> Richard

<Had to wait until I got home - was too busy at the day job to respond
;) >

I don't have any information on the buffers, but the header you have
probably runs out of steam at around a few MHz. If you have the
schematic for your dev. board , send it to me (you can find my email
via my profile) and I'll check the ratings on the buffers (if they
exist). I'll consider this one of my good deeds[tm] for the week :)

A two layer PCB (as noted by the esteemed Bill) may be ok with careful
layout. At a minimum, you'll have to have clean power to the A-D and
the appropriate clocks/framing etc., and then run the actual data back
across. Of course, keeping the signal to be sampled clean is an
absolute must (pretty pointless if you don't).

What resolution did you want to get? There are a number of solutions at
reasonably high speeds up to 24 bits (although they aren't cheap; say
$30 to $100s per unit depending on features, and that's in 1k qtys)

How up are you on A-D theory and practise? A device may say 24 bits but
you'll typically get an equivalent 21 bits or so due to the various
errors and noise (some manufacturers are good about putting such things
in their data sheets, others less so), and then there's some tricks of
the trade in the layout to ensure you get the best out of the device
(indeed, get anything useful at all).

The RF signal is going to be pretty low (to say the least) although
some newer devices designed for the task can deal with it - in that
case, you are looking at a different class of A-D with low noise PGAs
on the front end. A wideband RF amp and perhaps some band shaping may
be in order. There are simple solutions for that around, but it will
increase the complexity of the design somewhat.

Perhaps a digitally controlled mixer / IF stage might be a solution;
after all, you can do all sorts of band selection in hardware, and that
can be set up for the band you desire.

A lot of this will depend on exactly what you really need, of course.
If you want to do pre-amplification and selection, life becomes much
simpler (use a single IF output stage set by a mixer perhaps) that is
then sampled.

Cheers

PeteS

"PeteS" <PeterSmith1954@googlemail.com> wrote in message
news:1152639919.953010.283430@p79g2000cwp.googlegroups.com...
>
> A two layer PCB (as noted by the esteemed Bill) may be ok with careful
> layout.

If you try to do a 2-layer PCB for high-speed ADC/DAC you are on your own
with zero support from manufacturer. The chip pinouts are designed in the
assumption of existence of GND and PWR planes. I don't beleive one can get
advertised performance of a high-speed ADC/DAC using a 2-layer board. One
will be lucky if it will function at all...

> What resolution did you want to get? There are a number of solutions at
> reasonably high speeds up to 24 bits (although they aren't cheap; say
> $30 to $100s per unit depending on features, and that's in 1k qtys)

There no ADCs on the market with more than 14 bits that can cover the
requested band of 450 MHz.  If oversampling is a requirement then you won't
even find a 12 bit device that can do it. Perhaps 10, or 8 for sure, but not
better.


/Mikhail

MM wrote:
> "PeteS" <PeterSmith1954@googlemail.com> wrote in message
> news:1152639919.953010.283430@p79g2000cwp.googlegroups.com...
> >
> > A two layer PCB (as noted by the esteemed Bill) may be ok with careful
> > layout.
>
> If you try to do a 2-layer PCB for high-speed ADC/DAC you are on your own
> with zero support from manufacturer. The chip pinouts are designed in the
> assumption of existence of GND and PWR planes. I don't beleive one can get
> advertised performance of a high-speed ADC/DAC using a 2-layer board. One
> will be lucky if it will function at all...
>
> > What resolution did you want to get? There are a number of solutions at
> > reasonably high speeds up to 24 bits (although they aren't cheap; say
> > $30 to $100s per unit depending on features, and that's in 1k qtys)
>
> There no ADCs on the market with more than 14 bits that can cover the
> requested band of 450 MHz.  If oversampling is a requirement then you won't
> even find a 12 bit device that can do it. Perhaps 10, or 8 for sure, but not
> better.
>
>
> /Mikhail

I wasn't referring to the 450MHz rate :)

That was a 'wish'. I said 'reasonably high speeds' simply because the
OP seems to be open to suggestions. That said, I haven't seen better
than 10 bit resolution at 450 MHz (which, unless you are undersampling,
implies almost 1GS/s rates).

Cheers

PeteS