MIG DDR2 controller does not work (reset problems?)

>> As I said before the data compare module fails so it could be a signal
>> integrity problem which casuses the read out data to be corrupt.
> 
> Or, the read could be correct and the write could be wrong. It's kind of
> hard to tell that if you aren't getting past Comp_Done. You should
> probably look at the data going to and from the RAM, to see what's going
> on. Maybe there's a stuck bit, or maybe data from one bank is wrong but
> the rest are right. There are a lot of possibilities. It will take some
> investigating with ChipScope to figure out what's going on.
> 

Be aware than when putting chipscope and looking at we / cas / ras ...
you might prevent the tools to put the last register into the IOB and
then you have bad timings ...

So if it's the case, you are actually creating a problem with chipscope
and not debugging the real one ...

Checkout the timing report to see if the clock-to-out of the ddr_clk and
the control signals and the address leads to a valid timing.



    Sylvain