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Introducing picosecond delay between two output signals

Started by axr0284 March 7, 2007
Hi,
 I would like to know what are the common methods of introducing
delays as low as 10ps between two outputs in an FPGA. I do not
currently have a specific FPGA in mind. I am just looking for a
general answer.

 I know there are DCMs but this usually adds jitter and one needs to
wait for the DCM output to phase lock before the signal is stable and
it might take too long in our case. Basically I would want to power up
a board and have the delay be set in as short a time as possible. I
also need to minimise jitter to a minimum so that the two signals are
NEVER high at the same time. Thanks for any answer.
Amish

Amish,

The only method I am aware of is hand routing.  10ps is too small to
really be able to hold to in all cases.  With 35ps p-p jitter (minimum)
in any FPGA, and +/- 10 ps route matching (due to process variations
chip to chip), this may be impossible.

Austin

axr0284 wrote:
> Hi, > I would like to know what are the common methods of introducing > delays as low as 10ps between two outputs in an FPGA. I do not > currently have a specific FPGA in mind. I am just looking for a > general answer. > > I know there are DCMs but this usually adds jitter and one needs to > wait for the DCM output to phase lock before the signal is stable and > it might take too long in our case. Basically I would want to power up > a board and have the delay be set in as short a time as possible. I > also need to minimise jitter to a minimum so that the two signals are > NEVER high at the same time. Thanks for any answer. > Amish >
"axr0284" <axr0284@yahoo.com> wrote in message 
news:1173304789.265305.168410@p10g2000cwp.googlegroups.com...
> Hi, > I would like to know what are the common methods of introducing > delays as low as 10ps between two outputs in an FPGA. I do not > currently have a specific FPGA in mind. I am just looking for a > general answer. > > I know there are DCMs but this usually adds jitter and one needs to > wait for the DCM output to phase lock before the signal is stable and > it might take too long in our case. Basically I would want to power up > a board and have the delay be set in as short a time as possible. I > also need to minimise jitter to a minimum so that the two signals are > NEVER high at the same time. Thanks for any answer. > Amish
The jitter you get from having the FPGA in your signal path will far outweigh the delay difference you're looking for. To get delay resolution down to about 100 ps in the Spartan 3 family devices, for instance, carry chains can be manipulated in interesting ways. To get below 10 ps resolution, you really need a precision external circuit. For arbitrary tunable delays, I've worked with I/Q modulators in the past to generate a phase-shifted clock with sub-degree granularity (though not necessarily sub-degree precision) using DACs and RF devices. You can easily achieve 10 ps granularity through this external clock control; it makes it easier to keep the edges clean when the timing edges don't rely on the FPGA. - John_H
On Mar 7, 9:59 pm, "axr0284" <axr0...@yahoo.com> wrote:
> Hi, > I would like to know what are the common methods of introducing > delays as low as 10ps between two outputs in an FPGA. I do not > currently have a specific FPGA in mind. I am just looking for a > general answer. > > I know there are DCMs but this usually adds jitter and one needs to > wait for the DCM output to phase lock before the signal is stable and > it might take too long in our case. Basically I would want to power up > a board and have the delay be set in as short a time as possible. I > also need to minimise jitter to a minimum so that the two signals are > NEVER high at the same time. Thanks for any answer. > Amish
Actually, in theory I think you would be able to introduce delays in the order of 10ps. However controlling these is totally different matter. Back in the day, and I have to say for the record that I'm not that old, we used to introduce delays using the old fashioned RC tau way. So you might be able to relay certain bank or I/O by adding carefully calibrated RC network. Having said that, I don't think you would be able to have tight control over the timing simplying because what you'r asking more is more that what component imperfections can offer you. Another thing to keep in mind is the drive introduced by your measing device.
Signal propagation velocityon a pc-board is fairly stable and well-
controlled at half the speed of light, i.e. 6 inches or 15 cm per
nanosecond.
You are asking for 1% of that, so figure 60 mil/10 ps or 1.5 mm/10 ps.
Pretty small !
Peter Alfke

On Mar 7, 1:59 pm, "axr0284" <axr0...@yahoo.com> wrote:
> Hi, > I would like to know what are the common methods of introducing > delays as low as 10ps between two outputs in an FPGA. I do not > currently have a specific FPGA in mind. I am just looking for a > general answer. > > I know there are DCMs but this usually adds jitter and one needs to > wait for the DCM output to phase lock before the signal is stable and > it might take too long in our case. Basically I would want to power up > a board and have the delay be set in as short a time as possible. I > also need to minimise jitter to a minimum so that the two signals are > NEVER high at the same time. Thanks for any answer. > Amish
"axr0284" <axr0284@yahoo.com> wrote in message 
news:1173304789.265305.168410@p10g2000cwp.googlegroups.com...
> Hi, > I would like to know what are the common methods of introducing > delays as low as 10ps between two outputs in an FPGA. I do not > currently have a specific FPGA in mind. I am just looking for a > general answer.
A transmission line external to the FPGA of the appropriate length would be about the best approach for something that small. Kevin Jennings
Austin,

> With 35ps p-p jitter (minimum) in any FPGA...
I am currently designing some circuitry that needs to have jitter as low as possible, therefore this spec is most interesting for me. Are you talking about jitter introduced by DCMs or does ANY logic contained in an FPGA exhibit this jitter even when clocked with a low jitter clock. I have a 0.8 ps RMS jitter clock source available (DS4077). If the logic that I would like to clock with it would make a 35 ps pp minimum jitter out of it this would be a sheer catastrophe for me! Best regards Ulrich Bangert "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag news:esndg3$6os2@cnn.xsj.xilinx.com...
> Amish, > > The only method I am aware of is hand routing. 10ps is too small to > really be able to hold to in all cases. With 35ps p-p jitter (minimum) > in any FPGA, and +/- 10 ps route matching (due to process variations > chip to chip), this may be impossible. > > Austin > > axr0284 wrote: > > Hi, > > I would like to know what are the common methods of introducing > > delays as low as 10ps between two outputs in an FPGA. I do not > > currently have a specific FPGA in mind. I am just looking for a > > general answer. > > > > I know there are DCMs but this usually adds jitter and one needs to > > wait for the DCM output to phase lock before the signal is stable and > > it might take too long in our case. Basically I would want to power up > > a board and have the delay be set in as short a time as possible. I > > also need to minimise jitter to a minimum so that the two signals are > > NEVER high at the same time. Thanks for any answer. > > Amish > >
Ulrich Bangert wrote:
> Austin, > >> With 35ps p-p jitter (minimum) in any FPGA... > > I am currently designing some circuitry that needs to have jitter as low as > possible, therefore this spec is most interesting for me. Are you talking > about jitter introduced by DCMs or does ANY logic contained in an FPGA > exhibit this jitter even when clocked with a low jitter clock. I have a 0.8 > ps RMS jitter clock source available (DS4077). If the logic that I would > like to clock with it would make a 35 ps pp minimum jitter out of it this > would be a sheer catastrophe for me!
Someone else posted a similar question a few months ago, also asking about the feasibility of using FPGAs to work with 10ps-class events. Back then, all the local experts agreed that the routing fabric inside FPGAs will add many times this much jitter to any signal passing through it, even if the FPGA is only doing a direct routing from one IOB to another. Dedicated high-precision time bases are heavily shielded, temperature-controlled, built with highly specialized single-function low-noise ASICs fed with extensively regulated/filtered power supplies, etc., none of which applies to FPGA in a remotely comparable scale. On top of all the wonderful external noise sources such as radio interference, radiations, magnetic and capacitive coupling with the surroundings, etc., FPGAs generate their own heat, their own electromagnetic noises and all the other wonderful junk that spews jitter all over the fabric. Keep in mind that each electron moving through the FPGA adds its own tiny bit of noise and jitter while each transistor happily amplifies the noise of every electron bumping into its gate and that there are millions of transistors in the smallest modern FPGAs. You might have better luck by looking at the smallest CPLDs you can find: much fewer transistors, much less on-chip hardware, much simpler routing fabric, etc., this means much less internal noise and much fewer routing uncertainties but also pretty much no chance to do routing tricks to tweak timings. Maybe an hypothetical Virtex 7 would be able to do 10ps... but by the time these materialize, people will be posting here to ask for sub-ps precision and we'll have to tell them to wait for the Virtex 11.
Thanks for all the answers. I guess using an external component might
be more appropriate in this case. We used to use the AD9501 but it's
going obsolete thus the problem. Anyways I'll keep digging for a
solution. Thanks,
Amish


axr0284 wrote:
> Thanks for all the answers. I guess using an external component might > be more appropriate in this case. We used to use the AD9501 but it's > going obsolete thus the problem. Anyways I'll keep digging for a > solution. Thanks, > Amish
You can use the FPGA to do all the random logic you need on the signal but you must then *reclock* the signal external to the FPGA with your high precision clock. The output from the FPGA will be "sloppy" compared to your sub-picosecond jitter. A reclocked output will restore your extrememly low jitter performance.