LVDS termination scheme to nonstandard ribbon cable

Symon,

Wrong solution.

Using the _DT internal differential termination, the driver will see 100 
ohms in parallel with 5 pF (10pF in series with 10 pF).

If you SIMULATE this load, you will find that since the capacitance is 
directly across the 100 ohms, the receive signal is just fine.

Any reflections are absorbed by the 100 ohm driver (gee?  I wonder what 
genius thought of doing this?).

The rise times from the driver are moderate, and adequate, so 
mis-matches don't jump up and make life difficult, and cross talk is 
reduced.

Some folks have lightning fast drivers, which cross talk like crazy, and 
even their "lower" input C looks awful, as a signal with 2X the rise 
makes even 3pF look really bad.

"The system is the solution."  Driver, termination, line, receiver, all 
have to be considered.  I know, you, personally have issue with the 
solution, but, face it, Virtex family has been an astounding success: 
and TO THIS DAY, we are the only ones with 65nm product, shipping (at 
all) production parts.  ONE YEAR as of May 5th....

Think of all those sockets we are being designed into.  All of those 
LVDS interfaces working.  Literally tens of millions of them.

Do we have room to improve?  Of course.  But, any improvement is 
weighted against its benefits.  Make the input less capacitive has no 
benefit (other than you would immediately post "see!  I told you!" and I 
would not have to reply to this issue anymore).

What might be a better item to work on, rather than spend time on 
something that "ain't broke?"

Oh, did I mention how ecstatic we are that we have a one year lead on 65nm?

Austin

"Symon" <symon_brewer@hotmail.com> wrote in message 
news:f349ou$ppq$1@aioe.org...
>>
> It is possible to match even Xilinx's hideous 10pF receiver pins. Here's 
> an example from Xilinx's own consultant's website:-
> http://sigcon.com/Pubs/edn/ConstantRTermination.htm
>
> HTH, Syms.

This kind of approach certainly isn't obvious.

The reflections will *certainly* be much better.  Heck, the line can be 
probed and a good signal seen just about anywhere along the transmission 
line (assuming the probe doesn't introduce problems).

What should be noted is that - while there are no reflections and the end of 
the transmission line will see a superb voltage slow thanks to the R-only 
termination, this clean transition sees a series Zo impedance between it and 
the capacitor.

For a standard parallel Zo termination to a Zo characteristic impedance 
transmission line, the effective source is half the drive voltage through a 
Zo/2 impedance into the capacitor.  If there is no capacitance, the 
transition is gorgeous at the receiver.

For the termination scheme suggested, the point where the transition line 
sees the resistance is the same half-voltage swing.  Trouble here is that 
the equivalent series impedance to the capacitor is no longer fed by a half 
voltage with Zo/2 equivalent series impedance, but now a half voltage with a 
Zo series impedance.

If it's important to not have reflections, the R-only equivalent termination 
is superb.
If it's important to have the high slew rate, the standard termination with 
the associated pin capacitance is the way to go because the reflection 
*will* be absorbed by the transmitter's impedance if it's properly matched.

Signal Integrity *at the pin* is what's important and where a monte-carlo SI 
analysis will show which approach provides a cleaner interface in the end.

For this implementation where the speed is low, the extra 250 ps of RC time 
constant (it's C/2 for a differential signal) will probably provide 
excellent results.

- John_H 

"austin" <austin@xilinx.com> wrote in message 
news:f34blr$62p3@cnn.xilinx.com...
<snip>
> Without running the simulator, it is a complete waste of time to suggest 
> anything as a "solution" to this question.
<snip>

No need to get <snip>py.  There were many successful high speed designs 
before SI got the usable, affordable tools available today.  Without a 
fundamental understanding of what DOES affect signal fidelity, we doom our 
engineering future to shotgun hacks at "trying" to get the signals to 
perform well.

Since we have the SI tools available now in a way they weren't available a 
decade ago, quick analysis of alternatives can be pursued.  To suggest that 
fundamental knowledge be tossed out since there's a tool available is the 
short-sided view that often comes with the frustration of trying to 
communicate your point.

Please don't ask engineers to avoid learning the basics of delivering good 
signal integrity just because the tools are available to avoid doing the 
heavy mental lifting.  When's the last time you gave someone $22 for a $17 
charge expecting to get a $5 bill back and they stare at you like you're 
nuts.  "But it's only $17."  The crutch of calculators and cash registers 
have crippled much of a generation.  Lets keep engineering steeped in 
fundamentals and use the tools as they're meant: as tools.

- John_H 

"austin" <austin@xilinx.com> wrote in message 
news:f34blr$62p3@cnn.xilinx.com...
> Symon,
>
> Yes, I know what the author of the post is trying to do.
>
> Yes, Hyperlynx has built in models for a number of ribbon cables.
>
> Without running the simulator, it is a complete waste of time to suggest 
> anything as a "solution" to this question.
>
> Now that I have spent three times longer than I would have solving it with 
> the simulator, it appears that we have paid for the simulator, once again.
>
> GET IT? (I know you do, Symon).
>
> Austin

Hi Austin,
I do so enjoy our little chats! I also know that you're a big fan of 
simulation, and I totally agree it's a great tool. (Oh, and BTW, thanks for 
the pointer, I didn't realise that some ribbon cables were included in 
Hyperlynx, that's cool! Although, I fear the OP's cable is not included.)
My only comment is that some people are actually interested in the 
mechanisms at work. I'd say it's important to learn that first, and then use 
the simulator.
All the best, Syms. 

"austin" <austin@xilinx.com> wrote in message 
news:f34cle$6381@cnn.xilinx.com...
> Symon,
>
> Wrong solution.
>
> Using the _DT internal differential termination, the driver will see 100 
> ohms in parallel with 5 pF (10pF in series with 10 pF).
>
> If you SIMULATE this load, you will find that since the capacitance is 
> directly across the 100 ohms, the receive signal is just fine.
>
> Any reflections are absorbed by the 100 ohm driver (gee?  I wonder what 
> genius thought of doing this?).
>
We've been here before. I'll explain again. Remember that the OP is driving 
the line from a S3. So the 100 ohm driver has 5pf across it. Oh dear, the 
same reflection mechanism as at the receiver!
>
> The rise times from the driver are moderate, and adequate, so mis-matches 
> don't jump up and make life difficult, and cross talk is reduced.
>
Of course they're moderate, they have to charge up a 5pF cap. That's not a 
good thing, no matter how you spin it! It's only adequate if your 
application needs a moderate rise time!?
>
> Some folks have lightning fast drivers, which cross talk like crazy, and 
> even their "lower" input C looks awful, as a signal with 2X the rise makes 
> even 3pF look really bad.
>
So, I think on all my future high speed designs I'll add on extra capacitors 
to the drivers, you make it sound such a great idea! (Apologies for the 
sarcasm)
>
> "The system is the solution."  Driver, termination, line, receiver, all 
> have to be considered.  I know, you, personally have issue with the 
> solution, but, face it, Virtex family has been an astounding success: and 
> TO THIS DAY, we are the only ones with 65nm product, shipping (at all) 
> production parts.  ONE YEAR as of May 5th....
>
> Think of all those sockets we are being designed into.  All of those LVDS 
> interfaces working.  Literally tens of millions of them.
>
> Do we have room to improve?  Of course.  But, any improvement is weighted 
> against its benefits.  Make the input less capacitive has no benefit 
> (other than you would immediately post "see!  I told you!" and I would not 
> have to reply to this issue anymore).
>
> What might be a better item to work on, rather than spend time on 
> something that "ain't broke?"
>
> Oh, did I mention how ecstatic we are that we have a one year lead on 
> 65nm?
>
> Austin

Wow, what brought that on? I'm sorry but for some reason I kept seeing Tom 
Cruise on the couch when I was reading that! Ever thought of switching to 
de-caf? :-) (Just kidding!!) Anyway, we've been through this before, we're 
never gonna agree, your loyalty to Xilinx is too strong for that (kidding 
again!), but anyone who's interested can search back through comp.arch.fpga 
and decide for themselves whether high speed outputs and receivers are 
compromised by pin capacitance.
Cheers, Syms. 

"John_H" <newsgroup@johnhandwork.com> wrote in message 
news:135be6pdo0nn37e@corp.supernews.com...
> "Symon" <symon_brewer@hotmail.com> wrote in message 
> news:f349ou$ppq$1@aioe.org...
>>>
>> It is possible to match even Xilinx's hideous 10pF receiver pins. Here's 
>> an example from Xilinx's own consultant's website:-
>> http://sigcon.com/Pubs/edn/ConstantRTermination.htm
>>
>> HTH, Syms.
>
>
> If it's important to not have reflections, the R-only equivalent 
> termination is superb.
> If it's important to have the high slew rate, the standard termination 
> with the associated pin capacitance is the way to go because the 
> reflection *will* be absorbed by the transmitter's impedance if it's 
> properly matched.
>
> Signal Integrity *at the pin* is what's important and where a monte-carlo 
> SI analysis will show which approach provides a cleaner interface in the 
> end.
>
> For this implementation where the speed is low, the extra 250 ps of RC 
> time constant (it's C/2 for a differential signal) will probably provide 
> excellent results.
>
> - John_H
>
Hi John,
Neatly summarised!
Thanks, Syms. 

Symon,

We agree to disagree.

I would hope that it is clear that the Xilinx solution works just fine.

There are just far too many working pcbs out there to suggest otherwise.

I have already agreed it could be better, but if it works, why bother?


As for loyalty to Xilinx, I am trying to be an engineer:  facts, facts, 
facts.

Fact: input Z (and output Z) = 100 ohms + 5pf
Fact: risetime is adequate for the job (too fast is actually a bad 
thing, too slow just mens you can't operate at very high rates, parts 
meet their specifications)
Fact: Symon hates having any C in parallel with the termination.
Fact: All terminations have some C.
Fact: Symon and I do not agree.

Austin

John,

In no way did I imply that engineers should not learn about SI.

But, I can not require SI knowledge, either.

That is why we have IO standards (cookbook recipes).

Without a degree in E&M theory, I would argue that you can't really 
understand what is going on.

Well, a suppose a physicist might be capable of recognizing Maxwell's 
equations, but as far as I know, only those who have actually set up, 
and solved these equations, have the fundamental knowledge that is required.

There are many who have practical knowledge (experience), and that 
sometimes passes for understanding.

Anyone else is someone who is just pretending they have the knowledge.

And that is just fine:  just as we can not ask that all users of FPGAs 
know everything about heat transfer, we recognize that the team who are 
using the FPGA will require some support for those specialties that they 
lack.

Austin

Symon,

I agree.  For those for whom SI is a mystery, learn something today:  go 
read up on SI.

Austin

On Thu, 24 May 2007 07:23:01 -0700, austin <austin@xilinx.com> wrote:

>All,
>
>I suppose suggesting that the question could be answered in less than 10 
>minutes using a SIGNAL INTEGRITY simulator would just be silly?
>
>I am absolutely amazed at how much time, money, and energy is wasted 
>just because a SI simulator is "expensive."
>
>One respin of a pcb is MORE $$$ than buying the SI simulator tool.
>
>Mentor's Hyperlynx(tm) simulator is my favorite, but Cadence has their 
>tool which might be more to some folks liking (it is integrated with the 
>PCB layout stuff).
>
>So, how about it?  Invest in something that will save you enough money 
>to pay for it the first time you do not screw up.
>
>Submit a hotline webcase, and ask for a "what if" SI simulation.  That 
>way you will get a free example of (one) solution to your problem.
>
>
>One comment: matching the transmitter impedance is a good idea, as a 
>perfect match at the receiver is impossible (perfect may happen in 
>textbooks, but not in real life).
>

Does an LVDS transmitter have an impedance? The ones I've played with
seem to behave like current sources; unloaded, the diff outputs swing
(slowly!) almost rail-to-rail. That said, presenting the transmitter
with an equivalent 100 ohm net diff load will normalize the swing to
standard levels and speed things up a bit as compared to letting them
see a 173 or whatever diff load.

John