verilog parser question about `defines

I have a set of verilog files that uses `defines.  The same `define is
applied to each file to select which code to use.

Is there a way to setup Xilinx ISE so that when processing all verilog
files it assumes that a certain `define has been defined ?

On Wed, 25 Jul 2007 02:10:00 -0700, raphfrk <raphfrk@netscape.net>
wrote:

>I have a set of verilog files that uses `defines.  The same `define is
>applied to each file to select which code to use.
>
>Is there a way to setup Xilinx ISE so that when processing all verilog
>files it assumes that a certain `define has been defined ?

vlogcomp has a '-d' option:

evan 63 > vlogcomp
Release  - ISE Simulator Vlogcomp I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
...
Usage: vlogcomp {options}
...
 -d <macro>                 Define <macro>; The format of the <macro>
                            argument is <name>[=<val>] where <name> is
                            the name of the macro, and <val> is an
optional
                            value for the macro

Evan

On Jul 25, 8:38 am, Evan Lavelle <nos...@nospam.com> wrote:
> On Wed, 25 Jul 2007 02:10:00 -0700, raphfrk <raph...@netscape.net>
> wrote:
>
> >I have a set of verilog files that uses `defines.  The same `define is
> >applied to each file to select which code to use.
>
> >Is there a way to setup Xilinx ISE so that when processing all verilog
> >files it assumes that a certain `define has been defined ?
>
> vlogcomp has a '-d' option:
>
> evan 63 > vlogcomp
> Release  - ISE Simulator Vlogcomp I.31
> Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
> ...
> Usage: vlogcomp {options}
> ...
>  -d <macro>                 Define <macro>; The format of the <macro>
>                             argument is <name>[=<val>] where <name> is
>                             the name of the macro, and <val> is an
> optional
>                             value for the macro
>
> Evan


You can also add macros in the GUI under synthesis options
(Advanced) "Verilog Macros".  Use the same format for
definitions.  Use a vertical bar to separate multiple entries.

On Jul 26, 2:41 pm, Gabor <ga...@alacron.com> wrote:
> You can also add macros in the GUI under synthesis options
> (Advanced) "Verilog Macros".  Use the same format for
> definitions.  Use a vertical bar to separate multiple entries.

Thanks