Xilinx MIG DDR2 initialization problems

Started by Unknown July 27, 2007
I have used the MIG 1.72 tool to generate a memory interface for the
DDR2 SODIMM on the Xilinx ML501 board.

It works... sort of.

I am using the MIG synthesizable testbench as an indicator that the
memory and controller are functioning correctly (which does some reads
and writes to some addresses and makes sure they come back ok,
otherwise asserts its 'error' output).

The SIM_ONLY parameter, which disables the 200us power-on delay for
simulation has been causing me quite a bit of angst. When I
implemented the controller on the FPGA, phy_init_done is asserted and
the testbench gives no errors... iff SIM_ONLY is set to 1 (disable
200us delay).

When I set SIM_ONLY to 0 (i.e. the way it should be set for
implementation) one of the following happens:

1) phy_init_done is never asserted (memory init fails completely)
2) phy_init_done is asserted, but the testbench gives an error signal
3) After manually (pushbutton) generating a whole bunch of resets,
once in a while, it can be made to start up correctly

Not seeing how a 200us delay should have this effect, I did some
simulations and dug into the MIG code and discovered that setting the
SIM_ONLY parameter to 1 also causes stage 1 of the read calibration
routine to be skipped (would have been nice if it was documented
better). So, I set the SIM_ONLY flag back to 0 at the top level, and
then set it to 1 for the calibration module only. Now with the 200us
delay enabled, but stage 1 of the calibration routine is still being
skipped. With this arrangement, I see the right outputs (phy_init_done
is asserted, and no error from the testbench).

So I am left with a great many questions:

1) Why do things seem to work with stage 1 disabled? Is the default
good enough?
2) Why does stage 1 not succeed? I suspect perhaps a reset problem,
since resetting enough times will eventually land it in a functional
3) Why does the testbench usually fail if stage 1 succeeds, yet does
not fail ever when stage 1 is skipped?
4) How can I better probe to see where things are going wrong? What
might be good things to check?