So, I should use LOCKED and DO(1) to reset my DCM outside of FPGA, or I can reset DCM inside FPGA using another clock_input. Only these 2 solutions? Maybe I will do it in my next design, I cannot use DCM these time. Anyway, thanks, all of you.
DCM with instable clock
Started by ●November 22, 2007
Reply by ●November 28, 20072007-11-28
Reply by ●November 28, 20072007-11-28
Yes, Next time, be sure you have a local oscillator--your life will be far easier. Austin wxy0624@gmail.com wrote:> > So, I should use LOCKED and DO(1) to reset my DCM outside of FPGA, or > I can reset DCM inside FPGA using another clock_input. Only these 2 > solutions? > > Maybe I will do it in my next design, I cannot use DCM these time. > > Anyway, thanks, all of you.