DDR SDRAM demo for Spartan-3E starter kit?

I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16
-6T F).
Is there any *simple* demo that stores a picture bitmap in the builtin
DDR SDRAM and sends the bitmap to the VGA port continously ..?

Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL
used ..?
(Micron indicate that SDRAM can go as low as a few kHz in clock
frequency if needed)

I had a look at 3 Xilinx examples, but they seem almost more
complicated to get running than to code a sdram controller by myself.
Currently trying out opencores controller, but it seems to get stuck
synthesis.

What voltage is Vtt supposed to have for ddr sdram?, Is every resistor
needed, or can one do with a simpler interface if the dram <-> fpga
path is less than 1 inch/2 cm ..?

On Jan 5, 12:31 pm, posedg...@yahoo.com wrote:

> I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16
> -6T F).
> Is there any *simple* demo that stores a picture bitmap in the builtin
> DDR SDRAM and sends the bitmap to the VGA port continously ..?

I designed a DDR controller with wishbone interface for that board --
I know it works well
on a bunch of S3E-500 StarterKits, one S3E-1600 and I even use a
variant on the XUPV2P
Board.

But it's not ideally suited for your design, because it uses 2
BlockRAMs to cache access to the
DRAM -- If you can live with that....

See https://roulette.das-labor.org/bzrtrac/wiki/wb_ddr


   jb

On 5 Jan, 11:31, posedg...@yahoo.com wrote:
> I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16
> -6T F).
> Is there any *simple* demo that stores a picture bitmap in the builtin
> DDR SDRAM and sends the bitmap to the VGA port continously ..?
>
> Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL
> used ..?
> (Micron indicate that SDRAM can go as low as a few kHz in clock
> frequency if needed)
>
> I had a look at 3 Xilinx examples, but they seem almost more
> complicated to get running than to code a sdram controller by myself.
> Currently trying out opencores controller, but it seems to get stuck
> synthesis.
>
> What voltage is Vtt supposed to have for ddr sdram?, Is every resistor
> needed, or can one do with a simpler interface if the dram <-> fpga
> path is less than 1 inch/2 cm ..?

I am in the process of implementing a interface between microblaze and
Micron DDR SDRAM  using MPMC from the IP catalog provided in EDK 9.2i.
It has all the neccesary ports defined and support most DDR/DDR2
devices. I have not tested it yet, but it might be worth a try.

BR
rate

On Jan 5, 12:31=A0pm, posedg...@yahoo.com wrote:
> I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with46V32M16
> -6T F).
> Is there any *simple* demo that stores a picture bitmap in the builtin
> DDR SDRAM and sends the bitmap to the VGA port continously ..?

I've just bought the same board, and I'm interested in a DDR
controller
for the MT46V32M16. I've started coding one but I'm a novice in VHDL
and it may took a lot of time... maybe the eternity! ;)

> Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL
> used ..?
> (Micron indicate that SDRAM can go as low as a few kHz in clock
> frequency if needed)

Reading at page 24 of the device datasheet (Electrical Characteristics
and
Recommended AC Operating Conditions (-6, -6T, -75E)) it looks like
the
clock cycle time must be between 6 and 13 ns, meaning that the default
board clock (50 MHz) is not enough (you can use a DCM). Note 46 says
that it works below the JEDEC slowest operating frequency of 83 MHz
(13 ns ck =3D 76 MHz cf). Moreover consider that you should issue an
auto
refresh command every few (6 or 7) us.

As i said I'm beginning with VHDL, I'm just learning and what I'm
writing is
something to read/write a 32 bit value from/to a specific address,
that is, I'm not
looking for performance, just to basic functionality.

Joerg's solution should be nice, I'll take a look at the Verilog code
(BTW thanks),
I don't think I'll use the MicroBlaze soft processor because it's
commercial
and I'm just having fun with the FPGA in the spare time.

Regards

Andrew

On Jan 5, 7:14 pm, quark.flav...@gmail.com wrote:

> Joerg's solution should be nice, I'll take a look at the Verilog code
> (BTW thanks), I don't think I'll use the MicroBlaze soft processor because it's
> commercial and I'm just having fun with the FPGA in the spare time.

I ported the open source  Lattice Mico32 CPU to Xilinx and Altera
chips -- Comparable
to MicroBlaze (a bit larger, and a slightly lower f_max), buts it's
cross vendor RTL code
and complete open source [1].

Works fine with the wb_ddr controller on the said boards and powers
for example
 http://www.youtube.com/watch?v=4MGKhFIujM4


It's not the first complete open source SoC, and won't be the last one
-- But it's a capable
small footprint SoC plattform baeed on the wishbone interconnect. The
only thing I'm
currently really missing is a MMU.

  jb

 [1] https://roulette.das-labor.org/bzrtrac/wiki/soc-lm32

> I ported the open source  Lattice Mico32 CPU to Xilinx and Altera
> chips -- Comparable
> to MicroBlaze (a bit larger, and a slightly lower f_max), buts it's
> cross vendor RTL code
> and complete open source [1].

Sounds great! I've downloaded everything, the SoC, the wb-ddr
controller
and the simple ddr controller as well.

> Works fine with the wb_ddr controller on the said boards and powers
> for example
>  http://www.youtube.com/watch?v=4MGKhFIujM4

Cool app!

> It's not the first complete open source SoC, and won't be the last one
> -- But it's a capable
> small footprint SoC plattform baeed on the wishbone interconnect. The
> only thing I'm
> currently really missing is a MMU.

You have the controller, is the MMU hard to code?

Andrew

On Jan 6, 10:16 am, quark.flav...@gmail.com wrote:

> > I ported the open source  Lattice Mico32 CPU to Xilinx and Altera
> > chips -- Comparable to MicroBlaze (a bit larger, and a slightly lower f_max), buts it's
> > cross vendor RTL code and complete open source [1].
>
> Sounds great! I've downloaded everything, the SoC, the wb-ddr
> controller and the simple ddr controller as well.

I'd be happy if this could become a friendly cross vendor SoC
evironment, so please let me know if you're running into
difficulties.I understand that the absence of any documentation
for the build environment is a major hurdle :(

Hearing about success stories would be nice too :)

> > It's not the first complete open source SoC, and won't be the last one
> > -- But it's a capable small footprint SoC plattform baeed on the
> > wishbone interconnect. The only thing I'm currently really missing is
> > a MMU.
>
> You have the controller, is the MMU hard to code?

I'm currently evaluating how to proceed -- I think a soft loaded TLB
architecture is the way to go. But I need to understand precisely how
the caches work inside the LM32...

   jb

On Jan 5, 2:52 pm, j...@capsec.org wrote:
> On Jan 5, 12:31 pm, posedg...@yahoo.com wrote:
>
> > I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16
> > -6T F).
> > Is there any *simple* demo that stores a picture bitmap in the builtin
> > DDR SDRAM and sends the bitmap to the VGA port continously ..?
>
> I designed a DDR controller with wishbone interface for that board --
> I know it works well
> on a bunch of S3E-500 StarterKits, one S3E-1600 and I even use a
> variant on the XUPV2P
> Board.
>
> But it's not ideally suited for your design, because it uses 2
> BlockRAMs to cache access to the
> DRAM -- If you can live with that....
>
> Seehttps://roulette.das-labor.org/bzrtrac/wiki/wb_ddr

I downloaded and tried it. And it seems to work. At least data_ok and
data_ok_lt shines.
I just had to write a script to download from your Trac system and
rename 'DCM_SP' to DCM.
Now I'm trying to reverse engineer fml_memtest() so I can use it for
other things.
Is your code BSD licensed? (like NetBSD)

On Jan 6, 1:59=A0pm, j...@capsec.org wrote:
> I'd be happy if this could become a friendly cross vendor SoC
> evironment, so please let me know if you're running into
> difficulties.I understand that the absence of any documentation
> for the build environment is a major hurdle :(

Of course, I've tried to load the firmware and it runs smoothly
except for a long term error (ld0) that, as far as I've seen, occurrs
in the first few 5 - 8 read/write operations. I still have to dig into
the
problem, if I'll find something I'll report to you immediately. Maybe
it's
something about the DCM, a difference between the boards.
BTW the absence of documentation is not a problem at all since
I'm working on memory interface and your code is very good
and readable.

> Hearing about success stories would be nice too :)

Well, I'll do my best but I'm just learning, and I cannot say I've
ever done
something worthy as far, just experiments!

> I'm currently evaluating how to proceed -- I think a soft loaded TLB
> architecture is the way to go. But I need to understand precisely how
> the caches work inside the LM32...

Keep up the good work, I'll keep an eye on the progress of the
project.

Andrew

Hi,

> I downloaded and tried it. And it seems to work. At least data_ok and
> data_ok_lt shines.

Good -- "*_lt" is the longterm variant which, once lit, is never
reset.
If "error_lt" does *not* lite up, everything is fine.

> I just had to write a script to download from your Trac system and
> rename 'DCM_SP' to DCM.

Strange, I remember DCM_SP is the DCM variant one should use in
Spartan3E... Can't remember for sure...

> Now I'm trying to reverse engineer fml_memtest() so I can use it for
> other things.

> Is your code BSD licensed? (like NetBSD)

I hereby place it under LGPL and will update the source code
accordingly soon.

I currently do not have the time to dig deeply into the HDL open
source
licensing issue -- but LGPL seems to fit the bill: you may use the
component wherever you like, without beeing forced to publish any
of your application...
But if you enhance the component itself, you're forced to "give back".


   j.