DDR SDRAM demo for Spartan-3E starter kit?

On Jan 8, 12:53=A0pm, j...@capsec.org wrote:

> Strange, I remember DCM_SP is the DCM variant one should use in
> Spartan3E... Can't remember for sure...

DCM_SP should be correct, it is the Spartan3E DCM.

Andrew

On Jan 8, 9:59=A0am, quark.flav...@gmail.com wrote:
> On Jan 8, 12:53=A0pm, j...@capsec.org wrote:
>
> > Strange, I remember DCM_SP is the DCM variant one should use in
> > Spartan3E... Can't remember for sure...
>
> DCM_SP should be correct, it is the Spartan3E DCM.
>
> Andrew

Hello ,

I have been following your lm32 SOC thread on the fpgafaa for quiet
some time.I am new to the field of softcore/SOCs. I am interested in
an open core SOC to implement a Ethernet MAC controller for my
Spartan3E FPGA on my Spartan3E starter kit. That is when I came across
your work. I have to admit your spirit for open source, excellent job.
Now, that I have seen how sucessfuly you have ported the core to
Spartan3E FPGA i have a few questions.

(1) How do I implement the core on the Spartan3E FPGA? I downloaded
the SOC from "https://roulette.das-labor.org/~joerg/pkg/soc-lm32.zip,
and tired to complie the design on ISE9.1i. I got this error as the
compiler was missing a file. HDLCompilers:26 - "../../soc-lm32/soc-
lm32/boards/xilinx-s3esk/system.v" line 6 Could not find verilog
include file 'ddr_include.v'. I thought I can compile the design with
the system.v and system.ucf and I should be able to generate the bit
stream to load and prgram the FPGA with? Am I wrong in this
assumption. What am I missing here?? Are there any other files that is
supposed to go with this??

(2) Browsing your other folders, I find that there is one called
firmware that has a bootloader,ddr-phaser and hw-test? What are these
for?? Then, there is this whole bunch of folders that have the RTL .
What am i supposed to do with those??

Sorry to bother you with these pesky questions.

Thanks for your time and patients.