Ballpark PLB frequency

Hi,

I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am
somewhat conerned at the capabilities of the PLB bus in the system. I
require very high throughput and I'm conerned that the PLB will be the
main bottle neck in the design. I have two approches, use the PLB for
all traffic in the system, or offload some of that traffic to a
dedicated interface on the MPMC IP that Xilinx provides. I think,
eventually, for the very high bandwidth requirements, the MPMC
solution is the way to go, but I would like to get a ball park figure
of the capabilities of the PLB bus in general.

Given that the bus is 64bits, what would be a typically figure for PLB
bus frequency: 50, 100, 150, 200Mhz?

Would going to a high speed-grade FPGA alter this figure
significantly?

Thanks for any info,

Stephen

On 16 Feb., 13:44, Steve <stephe...@gmail.com> wrote:
> Hi,
>
> I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am
> somewhat conerned at the capabilities of the PLB bus in the system. I
> require very high throughput and I'm conerned that the PLB will be the
> main bottle neck in the design. I have two approches, use the PLB for
> all traffic in the system, or offload some of that traffic to a
> dedicated interface on the MPMC IP that Xilinx provides. I think,
> eventually, for the very high bandwidth requirements, the MPMC
> solution is the way to go, but I would like to get a ball park figure
> of the capabilities of the PLB bus in general.
>
> Given that the bus is 64bits, what would be a typically figure for PLB
> bus frequency: 50, 100, 150, 200Mhz?
>
> Would going to a high speed-grade FPGA alter this figure
> significantly?
>
> Thanks for any info,
>
> Stephen

VERY ballpark: 100MHz
sometimes higher too, ML505 ref design is 125MHz as example

Antti

So, around about 100Mhz?

It's fair to say that there is no defined upper limit on the clock
frequency in the EDK and that the maximum is basically determined by
ISE and the FPGA?

On 16 Feb, 16:30, Antti <Antti.Luk...@googlemail.com> wrote:
> On 16 Feb., 13:44, Steve <stephe...@gmail.com> wrote:
>
>
>
> > Hi,
>
> > I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am
> > somewhat conerned at the capabilities of the PLB bus in the system. I
> > require very high throughput and I'm conerned that the PLB will be the
> > main bottle neck in the design. I have two approches, use the PLB for
> > all traffic in the system, or offload some of that traffic to a
> > dedicated interface on the MPMC IP that Xilinx provides. I think,
> > eventually, for the very high bandwidth requirements, the MPMC
> > solution is the way to go, but I would like to get a ball park figure
> > of the capabilities of the PLB bus in general.
>
> > Given that the bus is 64bits, what would be a typically figure for PLB
> > bus frequency: 50, 100, 150, 200Mhz?
>
> > Would going to a high speed-grade FPGA alter this figure
> > significantly?
>
> > Thanks for any info,
>
> > Stephen
>
> VERY ballpark: 100MHz
> sometimes higher too, ML505 ref design is 125MHz as example
>
> Antti

Steve wrote:
> Hi,
> 
> I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am
> somewhat conerned at the capabilities of the PLB bus in the system.

> Given that the bus is 64bits, what would be a typically figure for PLB
> bus frequency: 50, 100, 150, 200Mhz?
>

I don't have the datasheets with me, but if you're running the PPC, then 
I think you're limited to certain multiples of PPC frequency. I ran the 
PPC at 300MHz and the PLB at 100MHz (on V2Pro and FX60).

I found the real issue was the implementation of the PLB Bus. There was 
a long combinatorial path that always failed timing, especially as more 
logic was added to the chip. I spent about a week with PlanAhead 
tweaking a layout that would consistently route with no errors.

> Would going to a high speed-grade FPGA alter this figure
> significantly?
Maybe not significantly, but a faster chip would give more timing margin.

---
Joe Samson
Pixel Velocity

Stephen,

I have had no trouble running a 2/3 full FX12-10 PLB bus with 4 devices 
at 100 Mhz.

If you have a lot of random control/status type register access from the 
CPU, you can offload that onto the DCR bus. And try to use as large as 
possible burst transfers on the PLB bus.

-Jeff

On 2008-02-16, Steve <stephenry@gmail.com> wrote:
>
> I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am
> somewhat conerned at the capabilities of the PLB bus in the system.

One sample:  V4 FX100-10, 75MHz PLB (connecting peripherals and MPMC2)
and 225MHz PPC.  The "theory" said 100MHz but that's what we got.  There
are higher speed grades that probably would have done 100MHz.

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

On Feb 17, 7:39=A0pm, Jeff Cunningham <j...@sover.net> wrote:
> Stephen,
>
> I have had no trouble running a 2/3 full FX12-10 PLB bus with 4 devices
> at 100 Mhz.
>
> If you have a lot of random control/status type register access from the
> CPU, you can offload that onto the DCR bus. And try to use as large as
> possible burst transfers on the PLB bus.
>
> -Jeff

I had FX12 totally full, with only 2 point-to-point PLB busses
connected to MPMC2 and PPC. For access to peripherals I used
exclusively DCR (low logic resources and high responsiveness), for
high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC.
I recommend NPI for very high DMA bandwidth.

Too bad that with EDK 9.2 the bus diversity is gone. You have to to
use PLB in all cases.

Cheers,

Ales

Guru wrote:
> I had FX12 totally full, with only 2 point-to-point PLB busses
> connected to MPMC2 and PPC. For access to peripherals I used
> exclusively DCR (low logic resources and high responsiveness), for
> high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC.
> I recommend NPI for very high DMA bandwidth.
> 
> Too bad that with EDK 9.2 the bus diversity is gone. You have to to
> use PLB in all cases.

Ales,
I'm still on 9.1. What bus diversity is changed in 9.2?
-Jeff

On 18 Feb., 17:20, Jeff Cunningham <j...@sover.net> wrote:
> Guru wrote:
> > I had FX12 totally full, with only 2 point-to-point PLB busses
> > connected to MPMC2 and PPC. For access to peripherals I used
> > exclusively DCR (low logic resources and high responsiveness), for
> > high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC.
> > I recommend NPI for very high DMA bandwidth.
>
> > Too bad that with EDK 9.2 the bus diversity is gone. You have to to
> > use PLB in all cases.
>
> Ales,
> I'm still on 9.1. What bus diversity is changed in 9.2?
> -Jeff

Microblaze 7.0 doesnt have OPB bus anymore.
was a real shock !

Old designs still can be used.
But all new systems have all new IP-Cores!

Antti

Antti wrote:
> On 18 Feb., 17:20, Jeff Cunningham <j...@sover.net> wrote:
> 
>>Guru wrote:
>>
>>>I had FX12 totally full, with only 2 point-to-point PLB busses
>>>connected to MPMC2 and PPC. For access to peripherals I used
>>>exclusively DCR (low logic resources and high responsiveness), for
>>>high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC.
>>>I recommend NPI for very high DMA bandwidth.
>>
>>>Too bad that with EDK 9.2 the bus diversity is gone. You have to to
>>>use PLB in all cases.
>>
>>Ales,
>>I'm still on 9.1. What bus diversity is changed in 9.2?
>>-Jeff
> 
> 
> Microblaze 7.0 doesnt have OPB bus anymore.
> was a real shock !
> 
> Old designs still can be used.
> But all new systems have all new IP-Cores!

  So much for the often-vaunted claims of 'design longevity' when
using SoftCPU cores then !  ;)
  Seems to have caught the Software Version Creep disease.... ?

-jg