Basic jitter from a CPLD (XC7500XL)

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:Le8%b.28417$ws.3197913@news02.tsnz.net...
<snip>
>   You can get a feel for jitter, and what matters, by doing some
> slew/threshold calculations.
>   eg consider a clock signal slewing at 1Volt/ns, and apply 10mv of
> threshold noise ( combined effects of Vcc noise ,Gnd bounce and
> crosstalk ) then purely the threshold modulation gives 10ps of jitter.
>   So, in CMOS a clean (linear) low noise power supply will help,
> as will short, shielded traces for Osc module -> PLD.
>   Faster edges from the Osc module will help (if you get the choice),
> and keeping any async, or random content signals 'away' from the clock
> divider portion of the PLD.
>   If you have a PLD+HC04, doing only /2, you could consider a HC1G79
> which is a tiny logic FF, to do both jobs. With NO other signals,
> and very low power, as well as a tiny package, this should have the
> lowest possible jitter.
>
>   In Audio, I believe jitter affects absolute noise floors, so you could
> look for that effect.
>   At 48KHz that's ~20us, so 20ns jitter is -60dB, and 20ps jitter
> is -120dB (numeric ratio only) - so it's not entirely snake
> oil, jitter numbers well under 1ns could have a measurable (if not
> audible:) impact.
>
>   For some real values quoted by process, see OnSemi's TND301
> http://www.onsemi.com/pub/Collateral/TND301-D.PDF
>
> -jg
>

Thanks Jim for your feedback. I will try to do some calculations as you
suggest, at least to know what ballpark we are likely to be in! That OnSemi
document looks very useful - I will read it properly as soon as I get a
moment.

I'm not quite sure what you mean about the HC1G79. To give you more info,
the CPLD buffers and proceses the digitial bitstream with the help of some
SRAM and other ICs and then spits it out. The output is then buffered via a
NOT gate to parallel NOT gates of the HC04 to provide enough drive for a
pulse transformer (I now realise I should have mentioned the gates and the
pulse transformer in the beginning, as they could also have a significant
effect on jitter - I was more concerned about the CPLD initially). I've
googled for HC1G79 but to no avail so far.

Jim

Jim wrote:
> Thanks Jim for your feedback. I will try to do some calculations as you
> suggest, at least to know what ballpark we are likely to be in! That OnSemi
> document looks very useful - I will read it properly as soon as I get a
> moment.
> 
> I'm not quite sure what you mean about the HC1G79. To give you more info,
> the CPLD buffers and proceses the digitial bitstream with the help of some
> SRAM and other ICs and then spits it out. The output is then buffered via a
> NOT gate to parallel NOT gates of the HC04 to provide enough drive for a
> pulse transformer (I now realise I should have mentioned the gates and the
> pulse transformer in the beginning, as they could also have a significant
> effect on jitter - I was more concerned about the CPLD initially).

When you use the slew model, you can appreciate any pulse transformer ( 
with its slow slew rates ) will likely have a big effect on jitter.

  Why is the transformer there, and do you work on both sides of it
- ie is the RX side your design ? Some care will be needed there,
to both keep Tsu/Th ok, and to minimise clock path degrade.

 >I've googled for HC1G79 but to no avail so far.

http://www.philipslogic.com/products/picogate/flipflops/

-jg

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:p2t%b.28542$ws.3212062@news02.tsnz.net...
> When you use the slew model, you can appreciate any pulse transformer (
> with its slow slew rates ) will likely have a big effect on jitter.
>
>   Why is the transformer there, and do you work on both sides of it
> - ie is the RX side your design ? Some care will be needed there,
> to both keep Tsu/Th ok, and to minimise clock path degrade.
>
>  >I've googled for HC1G79 but to no avail so far.
>
> http://www.philipslogic.com/products/picogate/flipflops/
>
> -jg

Thank you for the link Jim.

I do see what you mean about the slew rate of the transformer and its effect
on jitter. We are using a pulse transformer in the transmit side only. This
is to achieve galvanic isolation and is recommend for SPDIF output circuits
in the datasheets and documents we have, e.g.:
http://www.cirrus.com/en/pubs/proDatasheet/CS8405A-f.pdf  (800KB) page 34 -
consumer output circuit
http://www.cirrus.com/en/pubs/appNote/AN134-4.pdf  (70KB)
http://www.epanorama.net/documents/audio/spdif.html  (a collection of SPDIF
circuits from various sources)

The transformer is a Pulse Engineering PE-65812 and is recommended by Cirrus
Logic for SPDIF transmission. Hopefully this means jitter from the
transformer is kept as low as possible. Since the SPDIF outputs of all
consumer devices are meant to have a transformer in them (AFAIK), then they
must all have this problem?

On the other hand, I have also seen that many DIY audio geeks prefer a
direct connection with no transformer, I guess for exactly the reasons you
have suggested. However, since our product is for sale to the general
public, I like the idea of galvanic isolation to cover us in case of
incorrect connections by users and also failure within the unit itself that
could possibly damage their expensive equipment.

Jim

> I do see what you mean about the slew rate of the transformer and its effect
> on jitter. We are using a pulse transformer in the transmit side only. This
> is to achieve galvanic isolation and is recommend for SPDIF output circuits
> in the datasheets and documents we have, e.g.:
> http://www.cirrus.com/en/pubs/proDatasheet/CS8405A-f.pdf  (800KB) page 34 -
> consumer output circuit
> http://www.cirrus.com/en/pubs/appNote/AN134-4.pdf  (70KB)
> http://www.epanorama.net/documents/audio/spdif.html  (a collection of SPDIF
> circuits from various sources)
> 
> The transformer is a Pulse Engineering PE-65812 and is recommended by Cirrus
> Logic for SPDIF transmission. Hopefully this means jitter from the
> transformer is kept as low as possible. Since the SPDIF outputs of all
> consumer devices are meant to have a transformer in them (AFAIK), then they
> must all have this problem?
> 
> On the other hand, I have also seen that many DIY audio geeks prefer a
> direct connection with no transformer, I guess for exactly the reasons you
> have suggested. However, since our product is for sale to the general
> public, I like the idea of galvanic isolation to cover us in case of
> incorrect connections by users and also failure within the unit itself that
> could possibly damage their expensive equipment.

  This mentions Biphase modulation, and that requires clock recovery on 
the RX side. Thus you should choose low jitter Xtal source, (and a high
accuracy one could also help, if a digital PLL is used in the RX ) but 
the jitter introduced by the cpld will likely be insignifcant.
  I see the cirrus device specs MAX of 1ns jitter, which may or may not
include the transformer :)

  The RX clock recovery will lock into the centres of the data bi-phase 
bits, so final clock jitter will be determined mainly by their lock scheme.
  Of course, poor jitter, or frequency skew, on the data edges makes the
clock lock job harder...
-jg

Hi Philip!

Philip Freidin <philip@fliptronics.com> wrote:
> On Wed, 25 Feb 2004 13:06:30 -0000, "Jim" <jim@nospam.com> wrote:
>>
>>Is there a way of determining the maximum jitter of the output from the
>>CPLD? It's for digital audio so this info would be very useful.
>>
>>Many thanks,
>>
>>Jim
> 
> Jitter can be attenuated by using a PLL on the clock, but it has to be
> a PLL designed specifically for jitter attenuation.

Shouldnt it be possible to use a LC band pass filter (or even a crystal
filter) to remove spectral components far from the clock frequency?
This should improve at least the peak/rms ratio.
I am not sure if my idea is not too stupid. 
PLL design has also some difficulties.
> 
> If your goal was to have sub 200ps final jitter, I would suggest
> researching a structure such as:
> 
> Take the output of the CPLD and run it through a single FF outside the
> CPLD, such as a NL17SZ74US .
> 
For analogue filter a limiter amplifier or so is also necessary to
convert the filtered signal back to the "digital domain".
> Use extraordinary efforts for isolation from noise, such as sepparate
> local low noise LDO regulator with local bypassing for its power supply
> and appropriate issolation from ground noise of the rest of the system.
> 
This is always a good idea, for analogue and digital circuits as well.
In my experinence the influence of the power supply is often underestimated.
Especially when there some lack of time....
> Take your clock and pass it through a jitter attenuation PLL, with
> similar care with power supply and grounds. Use this (improved) clock
> for this external retiming flip flop.
> 
Best regards,

Christoph
> 
> Good luck,
> 
> Philip
> 
> 
> Philip Freidin
> Fliptronics

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:yvu%b.28550$ws.3214332@news02.tsnz.net...
> > I do see what you mean about the slew rate of the transformer and its
effect
> > on jitter. We are using a pulse transformer in the transmit side only.
This
> > is to achieve galvanic isolation and is recommend for SPDIF output
circuits
> > in the datasheets and documents we have, e.g.:
> > http://www.cirrus.com/en/pubs/proDatasheet/CS8405A-f.pdf  (800KB) page
34 -
> > consumer output circuit
> > http://www.cirrus.com/en/pubs/appNote/AN134-4.pdf  (70KB)
> > http://www.epanorama.net/documents/audio/spdif.html  (a collection of
SPDIF
> > circuits from various sources)
> >
> > The transformer is a Pulse Engineering PE-65812 and is recommended by
Cirrus
> > Logic for SPDIF transmission. Hopefully this means jitter from the
> > transformer is kept as low as possible. Since the SPDIF outputs of all
> > consumer devices are meant to have a transformer in them (AFAIK), then
they
> > must all have this problem?
> >
> > On the other hand, I have also seen that many DIY audio geeks prefer a
> > direct connection with no transformer, I guess for exactly the reasons
you
> > have suggested. However, since our product is for sale to the general
> > public, I like the idea of galvanic isolation to cover us in case of
> > incorrect connections by users and also failure within the unit itself
that
> > could possibly damage their expensive equipment.
>
>   This mentions Biphase modulation, and that requires clock recovery on
> the RX side. Thus you should choose low jitter Xtal source, (and a high
> accuracy one could also help, if a digital PLL is used in the RX ) but
> the jitter introduced by the cpld will likely be insignifcant.
>   I see the cirrus device specs MAX of 1ns jitter, which may or may not
> include the transformer :)
>
>   The RX clock recovery will lock into the centres of the data bi-phase
> bits, so final clock jitter will be determined mainly by their lock scheme
.
>   Of course, poor jitter, or frequency skew, on the data edges makes the
> clock lock job harder...
> -jg

In fact for the RX side I am using a Cirrus Logic digital audio receiver IC
with in-built PLL, CS8416:
http://www.cirrus.com/en/products/pro/detail/P1005.html
It talks about low-jitter clock recovery. I am using the recovered clock
from this IC to clock the CPLD. I was thinking I could maybe add another
CS8416 and a flipflop to reclock the CPLD's output before routing it through
the transformer, but didn't want to if not necessary (cost & extra
components & something else to worry about!)

-Jim