Why the second flip-flop in Virtex-6?

On Tue, 3 Feb 2009 18:14:23 +0100, "Jan Bruns" <testzugang_janbruns@arcor.de>
wrote:

>
>"Joseph H Allen":
>> Benjamin Couillard  <benjamin.couillard@gmail.com> wrote:
>>>On 3 f&#4294967295;v, 10:12, jhal...@TheWorld.com (Joseph H Allen) wrote:
>>>> I'm surprised that the Spartan-6 integrated memory controller does not support
>>>> DIMMs. Also surprised that there are no integrated memory controllers in
>>>> Virtex-6.
>>>>
>>>> Note the Virtex-6 Select-IO voltage range: only up to 2.5V! 2.5V is the
>>>> new 5V...
>>>
>>>3.3V is the new 5V you might say
>
>> No, 3.3V was the old new 5V.  The new new 5V is 2.5V.  Altera Straitx-IV
>> also does not support 3.3V I/O.
>
>Hm, ok, the old 5V-TTL logic devices pobably weren't compatible with
>tube-level logic.

Heh - maybe they were.

If you wanted a high current PSU in those days, it tended to be 6.3V AC.
Now if you multiply by sqrt(2), subtract a couple of diode drops, 10% for
regulation, 5% for line tolerance, a volt for ripple, and enough for a linear
regulator... you're about 5V.

- Brian

In article <9l9jo4dh2jaf45ko2vvadc51bn4chdcnt4@4ax.com>,
Brian Drummond  <brian@shapes.demon.co.uk> wrote:
>On Tue, 3 Feb 2009 15:12:41 +0000 (UTC), jhallen@TheWorld.com (Joseph H Allen)
>wrote:
>
>>I'm surprised that the Spartan-6 integrated memory controller does not support
>>DIMMs.  Also surprised that there are no integrated memory controllers in
>>Virtex-6.

>Reading between the lines here...

>At a guess the V6 I/O blocks are fast enough to support DDR memory quite well
>without special support - and that way you have the flexibility to support any
>configuration you need (modulo SSO limitations; the tools will handle those)

I'm thinking an integrated memory controller would be valuable in Virtex-6
because then designers would not have to go through the effort of using MIG. 
It works, but is still a lot of effort to make a high performance memory
interface.  Also why waste LUTs on a memory interface?  I want the LUTs for
my design, not for glue logic to make their chip work with SDRAM.  Finally,
DDR3 support is not really integrated in MIG.

-- 
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
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]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

-jg wrote:
>> It more a question of die space. 3.3v tolerant IO is huge in 40/45nm.
>> In V6 they are trying to reach the high end of IO and LUT counts. On
>> the other hand with S6 the LUT counts are not that high and also the IO
>> count is lower than in V6 so they can waste space for the IO.
> 
> Die Size, are you sure ?
> - My understanding is Oxide thickness is what primarily determines IO
> Voltage Specs.
> 
> Die area (PAD IO area) more determines drive current.

Oxide thickness is one parameter in the equation. As you mentioned drive
current affects also heavily the pad area, and for 3.3v that is a
problematic area. I should have said just 3.3v IO not 3.3v tolerant IO.
3.3v can be done in 40nm process without major tweaking, but you pay in
the IO size.

For example in CycloneIII (65nm part) the maximum drive current for 3.3v
LVCMOS IO is 2mA which is very small making the IO standard almost
unusable (8mA with LVTTL which is not so great either).

--Kim

On Feb 3, 8:12=A0am, jhal...@TheWorld.com (Joseph H Allen) wrote:
> I'm surprised that the Spartan-6 integrated memory controller does not su=
pport
> DIMMs. =A0Also surprised that there are no integrated memory controllers =
in
> Virtex-6.

If the memory controller is a hard version of what's in the EDK, you
won't want to use it ...

-a