Bidirectional Bus

On Sep 10, 1:18=A0am, nobody <cydrollin...@gmail.com> wrote:
> Antti,
>
> Do not want to raise any hackles, but you are correct about the
> demandperipherials knock off, perceptive. I talked with Bob Smith
> about a couple of things and he basically said go away, I understand
> and with no further ado I did. Here is a picture of my finished
> product,http://www.mediafire.com/?sharekey=3D923066edf8d516eeed24a2875c7f=
a58ee0...
>
> I agree about the so simple part, However there is something
> interesting in this problem I have described, I just have not found
> it.
>
> SPI works fine and is not part of the usb programming, indirect JTAG
> only.
>
> I am not sure how the FT245RL can strobe its own read line and produce
> a CCLK in order to load the data into FPGA, if you are willing to
> elaborate im willing to read.
>
> I went for a swim to clear my head it works every time.
>
> Will give your suggestions a closer look.
>
> I have so much completed on this board from absolutely nothing to 95%
> working it is a great project and will be taking this open source. I
> wonder why my work is not necessary?
>
> Antti, thanks for chatting not looking to raise any hackles, but am
> glad for the help.
>
> Cy Drollinger

Cy

pretty much NO ONE in the open-source community is inteterested in 4
layer PCB with S3E
ALL S3E board level products are DISCONTINUED by Xilinx
if Xilinx has discontinued, why do you want to promote something
Xilinx itself wants to forget?

your board is TOO expensive

option:

step 1:
take S3AN add LDO, and RJ45 jack and 100 mil header
PCB should be REAL simple and 2 layers only

step 2:
ask U2TOOL OEM pricing (coming soon www.u2tool.com )

step 3:
bundle items [1] and [2]

you can do step 2 before step 1 :)

Antti

Completion,

The FPGA never releases  the Global Three State(GTS) after done goes
high, described in DS312 pg. 107, because the fpga_cclk shuts down one
clock cycle to early. After the revision of taking out the need to
program while FPGA_initb is high gives the extra fpga_cclk needed to
release GTS signal and drives the High Z FPGA_d bus. One stinking
clock cycle who knew?

Sincerely,

Cy Drollinger

On Sep 10, 4:36=A0pm, nobody <cydrollin...@gmail.com> wrote:
> Completion,
>
> The FPGA never releases =A0the Global Three State(GTS) after done goes
> high, described in DS312 pg. 107, because the fpga_cclk shuts down one
> clock cycle to early. After the revision of taking out the need to
> program while FPGA_initb is high gives the extra fpga_cclk needed to
> release GTS signal and drives the High Z FPGA_d bus. One stinking
> clock cycle who knew?
>
> Sincerely,
>
> Cy Drollinger

You can change the order of the startup events in the bitgen
options.  I've have similar problems when using a micro to
load the FPGA and stopping as soon as DONE is high.  The
default startup sequence sets DONE high before releasing
GSR.  For a design with only one FPGA this is not necessary.
The intent is to synchronize startup of multiple devices
in a chain.

Regards,
Gabor

On Sep 10, 11:36=A0pm, nobody <cydrollin...@gmail.com> wrote:
> Completion,
>
> The FPGA never releases =A0the Global Three State(GTS) after done goes
> high, described in DS312 pg. 107, because the fpga_cclk shuts down one
> clock cycle to early. After the revision of taking out the need to
> program while FPGA_initb is high gives the extra fpga_cclk needed to
> release GTS signal and drives the High Z FPGA_d bus. One stinking
> clock cycle who knew?
>
> Sincerely,
>
> Cy Drollinger

Cy

this was actually OBVIOUS, I assumed you KNOW FPGA is configured AND
working
(this is not same as done=3D1)

it is always wise to send extra clocks after done=3D1... this is for me
common knowledge
i should have suggested this earlier, but i assumed you DID know that
FPGA was
actually driving the pins

btw bus conflict and non-driving bus can be seen as different with DSO
or even multimeter

Antti

On Sep 11, 12:17=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 10, 11:36=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
> > Completion,
>
> > The FPGA never releases =A0the Global Three State(GTS) after done goes
> > high, described in DS312 pg. 107, because the fpga_cclk shuts down one
> > clock cycle to early. After the revision of taking out the need to
> > program while FPGA_initb is high gives the extra fpga_cclk needed to
> > release GTS signal and drives the High Z FPGA_d bus. One stinking
> > clock cycle who knew?
>
> > Sincerely,
>
> > Cy Drollinger
>
> Cy
>
> this was actually OBVIOUS, I assumed you KNOW FPGA is configured AND
> working
> (this is not same as done=3D1)
>
> it is always wise to send extra clocks after done=3D1... this is for me
> common knowledge
> i should have suggested this earlier, but i assumed you DID know that
> FPGA was
> actually driving the pins
>
> btw bus conflict and non-driving bus can be seen as different with DSO
> or even multimeter
>
> Antti

Antti,

Do not beat yourself up about the OBVIOUS, you had a good suggestion
about the High "Z" bus and my problem when you asked me to isolate
this  feature on unused pins. I got more familiar with High Z
circuitry and its behavior, BTW Because it is written in Synthesis and
in a constraints file does not make it so, Synthesis can override
these as in defaults and preferences set within Synthesis.

Cy

On Sep 11, 5:38=A0pm, nobody <cydrollin...@gmail.com> wrote:
> On Sep 11, 12:17=A0am, "Antti.Luk...@googlemail.com"
>
>
>
> <antti.luk...@googlemail.com> wrote:
> > On Sep 10, 11:36=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
> > > Completion,
>
> > > The FPGA never releases =A0the Global Three State(GTS) after done goe=
s
> > > high, described in DS312 pg. 107, because the fpga_cclk shuts down on=
e
> > > clock cycle to early. After the revision of taking out the need to
> > > program while FPGA_initb is high gives the extra fpga_cclk needed to
> > > release GTS signal and drives the High Z FPGA_d bus. One stinking
> > > clock cycle who knew?
>
> > > Sincerely,
>
> > > Cy Drollinger
>
> > Cy
>
> > this was actually OBVIOUS, I assumed you KNOW FPGA is configured AND
> > working
> > (this is not same as done=3D1)
>
> > it is always wise to send extra clocks after done=3D1... this is for me
> > common knowledge
> > i should have suggested this earlier, but i assumed you DID know that
> > FPGA was
> > actually driving the pins
>
> > btw bus conflict and non-driving bus can be seen as different with DSO
> > or even multimeter
>
> > Antti
>
> Antti,
>
> Do not beat yourself up about the OBVIOUS, you had a good suggestion
> about the High "Z" bus and my problem when you asked me to isolate
> this =A0feature on unused pins. I got more familiar with High Z
> circuitry and its behavior, BTW Because it is written in Synthesis and
> in a constraints file does not make it so, Synthesis can override
> these as in defaults and preferences set within Synthesis.
>
> Cy

you can not change the io type with constraints.. only by RTL
you can change settings for unused pins with some settings
but the in/out/bidir is dictated by RTL code

Antti