SystemVerilog Verification Example using Quartus and ModelSim

Hello, I've been using the Quartus Simulator for many years and have
recently started learning about the SystemVerilog Verification. I was
hoping to find someone that has done this and is using Quartus. I am
new to ModelSim and I configure Quartus to launch ModelSim to run my
simulation. If anyone could provide a simple example of a program and
a Verification testbench I would very much appreciate it. I've been
reading Chris Spear's book SystemVerilog for Verification and would
like to see an example that works in Quartus. I'm still trying to get
a handle of what is a Generator, Agent, Drier, Monitor, and Checker,
terms found in Spear's book.

Thanks everyone,
joe

On Thu, 14 Jan 2010 12:48:23 -0800 (PST), jjlindula wrote:

>Hello, I've been using the Quartus Simulator for many years and have
>recently started learning about the SystemVerilog Verification. I was
>hoping to find someone that has done this and is using Quartus. I am
>new to ModelSim and I configure Quartus to launch ModelSim to run my
>simulation. If anyone could provide a simple example of a program and
>a Verification testbench I would very much appreciate it. I've been
>reading Chris Spear's book SystemVerilog for Verification and would
>like to see an example that works in Quartus. I'm still trying to get
>a handle of what is a Generator, Agent, Drier, Monitor, and Checker,
>terms found in Spear's book.

Note that you will need the enhanced version of ModelSim (Questa, 
or possibly Modelsim SE with various additional license features)
to run most of the new SystemVerilog verification features.
Chris Spear's book mainly describes verification architecture
using SystemVerilog's object-oriented programming features,
and those definitely require top-end features of the simulator
that you simply won't get in the cheaper or "student" editions.

If you do have access to a full version of Questa or Modelsim, 
you will also need to be aware that the examples in Spear's
book were written to run on Synopsys' VCS simulator.  Although
the SystemVerilog language is IEEE standardized, there remain
some differences among the simulators - and the book was written
a while ago, at a time when those differences were somewhat 
greater.  So don't be too surprised if you get compile errors 
for some examples - folk here will certainly be able to 
help straighten that out for you.

Also, take a look at the two big-name methodology websites
  www.vmmcentral.org  www.ovmworld.org
Both have downloads of toolkits, documentation and examples, 
and both have active user forums.
-- 
Jonathan Bromley

>On Thu, 14 Jan 2010 12:48:23 -0800 (PST), jjlindula wrote:
>
>>Hello, I've been using the Quartus Simulator for many years and have
>>recently started learning about the SystemVerilog Verification. I was
>>hoping to find someone that has done this and is using Quartus. I am
>>new to ModelSim and I configure Quartus to launch ModelSim to run my
>>simulation. If anyone could provide a simple example of a program and
>>a Verification testbench I would very much appreciate it. I've been
>>reading Chris Spear's book SystemVerilog for Verification and would
>>like to see an example that works in Quartus. I'm still trying to get
>>a handle of what is a Generator, Agent, Drier, Monitor, and Checker,
>>terms found in Spear's book.
>
>Note that you will need the enhanced version of ModelSim (Questa, 
>or possibly Modelsim SE with various additional license features)
>to run most of the new SystemVerilog verification features.
>Chris Spear's book mainly describes verification architecture
>using SystemVerilog's object-oriented programming features,
>and those definitely require top-end features of the simulator
>that you simply won't get in the cheaper or "student" editions.
>
>If you do have access to a full version of Questa or Modelsim, 
>you will also need to be aware that the examples in Spear's
>book were written to run on Synopsys' VCS simulator.  Although
>the SystemVerilog language is IEEE standardized, there remain
>some differences among the simulators - and the book was written
>a while ago, at a time when those differences were somewhat 
>greater.  So don't be too surprised if you get compile errors 
>for some examples - folk here will certainly be able to 
>help straighten that out for you.
>
>Also, take a look at the two big-name methodology websites
>  www.vmmcentral.org  www.ovmworld.org
>Both have downloads of toolkits, documentation and examples, 
>and both have active user forums.
>-- 
>Jonathan Bromley
>

And Janick Bergeron's "Verification Guild" site at
http://verificationguild.com/ is a great resource for SystemVerilog
verification information (and some good stuff for other languages).
	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

On Jan 15, 12:02=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Thu, 14 Jan 2010 12:48:23 -0800 (PST), jjlindula wrote:
> >Hello, I've been using the Quartus Simulator for many years and have
> >recently started learning about the SystemVerilog Verification. I was
> >hoping to find someone that has done this and is using Quartus. I am
> >new to ModelSim and I configure Quartus to launch ModelSim to run my
> >simulation. If anyone could provide a simple example of a program and
> >a Verification testbench I would very much appreciate it. I've been
> >reading Chris Spear's book SystemVerilog for Verification and would
> >like to see an example that works in Quartus. I'm still trying to get
> >a handle of what is a Generator, Agent, Drier, Monitor, and Checker,
> >terms found in Spear's book.
>
> Note that you will need the enhanced version of ModelSim (Questa,
> or possibly Modelsim SE with various additional license features)
> to run most of the new SystemVerilog verification features.
> Chris Spear's book mainly describes verification architecture
> using SystemVerilog's object-oriented programming features,
> and those definitely require top-end features of the simulator
> that you simply won't get in the cheaper or "student" editions.
>
> If you do have access to a full version of Questa or Modelsim,
> you will also need to be aware that the examples in Spear's
> book were written to run on Synopsys' VCS simulator. =A0Although
> the SystemVerilog language is IEEE standardized, there remain
> some differences among the simulators - and the book was written
> a while ago, at a time when those differences were somewhat
> greater. =A0So don't be too surprised if you get compile errors
> for some examples - folk here will certainly be able to
> help straighten that out for you.
>
> Also, take a look at the two big-name methodology websites
> =A0www.vmmcentral.org=A0www.ovmworld.org
> Both have downloads of toolkits, documentation and examples,
> and both have active user forums.
> --
> Jonathan Bromley

Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
that be okay?

On Jan 15, 2:20=A0am, "RCIngham" <robert.ingham@n_o_s_p_a_m.gmail.com>
wrote:
> >On Thu, 14 Jan 2010 12:48:23 -0800 (PST), jjlindula wrote:
>
> >>Hello, I've been using the Quartus Simulator for many years and have
> >>recently started learning about the SystemVerilog Verification. I was
> >>hoping to find someone that has done this and is using Quartus. I am
> >>new to ModelSim and I configure Quartus to launch ModelSim to run my
> >>simulation. If anyone could provide a simple example of a program and
> >>a Verification testbench I would very much appreciate it. I've been
> >>reading Chris Spear's book SystemVerilog for Verification and would
> >>like to see an example that works in Quartus. I'm still trying to get
> >>a handle of what is a Generator, Agent, Drier, Monitor, and Checker,
> >>terms found in Spear's book.
>
> >Note that you will need the enhanced version of ModelSim (Questa,
> >or possibly Modelsim SE with various additional license features)
> >to run most of the new SystemVerilog verification features.
> >Chris Spear's book mainly describes verification architecture
> >using SystemVerilog's object-oriented programming features,
> >and those definitely require top-end features of the simulator
> >that you simply won't get in the cheaper or "student" editions.
>
> >If you do have access to a full version of Questa or Modelsim,
> >you will also need to be aware that the examples in Spear's
> >book were written to run on Synopsys' VCS simulator. =A0Although
> >the SystemVerilog language is IEEE standardized, there remain
> >some differences among the simulators - and the book was written
> >a while ago, at a time when those differences were somewhat
> >greater. =A0So don't be too surprised if you get compile errors
> >for some examples - folk here will certainly be able to
> >help straighten that out for you.
>
> >Also, take a look at the two big-name methodology websites
> > =A0www.vmmcentral.org=A0www.ovmworld.org
> >Both have downloads of toolkits, documentation and examples,
> >and both have active user forums.
> >--
> >Jonathan Bromley
>
> And Janick Bergeron's "Verification Guild" site athttp://verificationguil=
d.com/is a great resource for SystemVerilog
> verification information (and some good stuff for other languages).
>
> --------------------------------------- =A0 =A0 =A0 =A0
> This message was sent using the comp.arch.fpga web interface onhttp://www=
.FPGARelated.com

Thanks everyone for your comments.

>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>that be okay?

I wouldnt of thought that version of Modelsim will work.

Jon	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

On Fri, 15 Jan 2010 07:32:13 -0800 (PST), jjlindula wrote:

[me]
>> using SystemVerilog's object-oriented programming features,
>> and those definitely require top-end features of the simulator
>> that you simply won't get in the cheaper or "student" editions.

[you]
>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>that be okay?

I'm afraid not.

You will probably find that quite a few of the SV design features
are fully supported in that version - interfaces, always_comb,
structs, .* port connection, that sort of thing - but I would
be astonished if you had access to any of the big-ticket
verification stuff such as classes and randomization.  To
find out, try these little examples.  Be sure to give the
files ".sv" extension, or alternatively use the -sv compile
option to the vlog command.

<example 1>
module enum_test;  // probably works OK
  typedef enum {first, second, third} ordinal;
  ordinal which;
  initial begin
    which = second;
    $display("this should print 'second': %s", which.name());
  end
endmodule

<example 2>
module random_test;  // I don't expect this to work in MSim AE
  integer i, ok;
  initial begin
    repeat (10) begin
      ok = randomize(i) with {i inside {1,2,4,8,16};};
      if (ok)
        $display("random value is %0d", i);
      else
        $display("randomization FAILED");
    end
  end
endmodule

<example 3> 
module struct_test; // this probably OK
  typedef struct {int a; bit b;} s_ab;
  s_ab ab;
  initial begin
    ab = '{15, 0};
    $display("ab.a should be 15: %0d", ab.a);
    $display("ab.b should be 0: %0d", ab.b);
  end
endmodule

<example 4>
module string_test;  // not sure about this one
  string s1, s2;
  int i;
  initial begin
    s1 = "hello";
    i = 7;
    $sformat(s2, "%s, i=%0d", s1, i);
    $display("Should print 'hello, i=7': %s", s2);
    $display("The word 'hello' has %0d characters", s1.len());
  end
endmodule

<example 5>
module class_test; // no chance of this working!
  class C;
    int a;
    string name;
    function new(string n = "unnamed", int v=0);
      name = n;
      a = v;
    endfunction
    function void print();
      $display("%s.a=%0d", name, a);
    endfunction
  endclass
  initial begin
    C c1 = new;
    C c2 = new("c2", 5);
    $display("Next line should say unnamed.a=0");
    c1.print();
    $display("Next line should say c2.a=5");
    c2.print();
  end
endmodule

All these examples run just fine in the full version.
-- 
Jonathan Bromley

In article <oi51l5dco9u5ncgo207pg8s8s4g6b0mb83@4ax.com>,
Jonathan Bromley  <jonathan.bromley@MYCOMPANY.com> wrote:
>On Fri, 15 Jan 2010 07:32:13 -0800 (PST), jjlindula wrote:
>
>[me]
>>> using SystemVerilog's object-oriented programming features,
>>> and those definitely require top-end features of the simulator
>>> that you simply won't get in the cheaper or "student" editions.
>
>[you]
>>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>>that be okay?
>
>I'm afraid not.
>
>You will probably find that quite a few of the SV design features
>are fully supported in that version - interfaces, always_comb,
>structs, .* port connection, that sort of thing - but I would
>be astonished if you had access to any of the big-ticket
>verification stuff such as classes and randomization.  To
>find out, try these little examples.  Be sure to give the
>files ".sv" extension, or alternatively use the -sv compile
>option to the vlog command.
>
<snipped (good!) examples>

Actually, modelsim SE supports a large set of SystemVerilog.
All the examples work except for example 2 with
Modelsim SE.  SE supports all of the "design" features
of SystemVerilog as well as SystemVerilog classes. 
You need Questa for the constraint solver and SystemVerilog
Assertions.  Which makes sense as that's the harder
problem to solve for tool vendors.  

Now, I'm using SE - which is NOT a "Starter Edition" as the OP indicated.
I thought the starter product was "DE" or something like that.

Your mileage may vary - Mentor likes to slice and dice their
product definition / licensing to (confusing) extremes... 

--Mark

> Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
> that be okay?

As the others have said probably not.

The OEM /Starter Editions are all knobbled a bit, they run at reduced
speed or functionality.

The base 'normal' spec of Modelsim is PE (Properly Expensive), this is
superceded by SE (Specially Expensive).


[Particularly here in the UK where tools prices seem to be the same in �
as the guys from the States get them in $ (�1 ~ $1.6)]



Nial. 

"Mark Curry" <gtwrek@sonic.net> wrote in message 
news:4b509c09$0$1597$742ec2ed@news.sonic.net...
> In article <oi51l5dco9u5ncgo207pg8s8s4g6b0mb83@4ax.com>,
> Jonathan Bromley  <jonathan.bromley@MYCOMPANY.com> wrote:
>>On Fri, 15 Jan 2010 07:32:13 -0800 (PST), jjlindula wrote:
>>
>>[me]
>>>> using SystemVerilog's object-oriented programming features,
>>>> and those definitely require top-end features of the simulator
>>>> that you simply won't get in the cheaper or "student" editions.
>>
>>[you]
>>>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>>>that be okay?
>>
>>I'm afraid not.
>>
>>You will probably find that quite a few of the SV design features
>>are fully supported in that version - interfaces, always_comb,
>>structs, .* port connection, that sort of thing - but I would
>>be astonished if you had access to any of the big-ticket
>>verification stuff such as classes and randomization.  To
>>find out, try these little examples.  Be sure to give the
>>files ".sv" extension, or alternatively use the -sv compile
>>option to the vlog command.
>>
> <snipped (good!) examples>
>
> Actually, modelsim SE supports a large set of SystemVerilog.
> All the examples work except for example 2 with
> Modelsim SE.  SE supports all of the "design" features
> of SystemVerilog as well as SystemVerilog classes.
> You need Questa for the constraint solver and SystemVerilog
> Assertions.

SVA (and PSL) are supported in Modelsim DE (much cheaper than SE/Questa and it 
runs under Linux :-), but you are correct regarding the rest.

Hans
www.ht-lab.com


> Which makes sense as that's the harder
> problem to solve for tool vendors.
>
> Now, I'm using SE - which is NOT a "Starter Edition" as the OP indicated.
> I thought the starter product was "DE" or something like that.
>
> Your mileage may vary - Mentor likes to slice and dice their
> product definition / licensing to (confusing) extremes...
>
> --Mark
>