SystemVerilog Verification Example using Quartus and ModelSim

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in 
message news:7rbm1tFrl4U1@mid.individual.net...
>> Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will
>> that be okay?
>
> As the others have said probably not.
>
> The OEM /Starter Editions are all knobbled a bit, they run at reduced
> speed or functionality.
>
> The base 'normal' spec of Modelsim is PE (Properly Expensive), this is
> superceded by SE (Specially Expensive).

:-)

>
>
> [Particularly here in the UK where tools prices seem to be the same in &#4294967295;
> as the guys from the States get them in $ (&#4294967295;1 ~ $1.6)]

That is indeed very annoying, Mentor is not the only one doing it.

http://www.amanwithapencil.com/adobe.html

Hans
www.ht-lab.com


>
>
>
> Nial.
> 

Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> writes:

> You will probably find that quite a few of the SV design features
> are fully supported in that version - interfaces, always_comb,
> structs, .* port connection, that sort of thing - but I would
> be astonished if you had access to any of the big-ticket
> verification stuff such as classes and randomization.  To
> find out, try these little examples.  Be sure to give the
> files ".sv" extension, or alternatively use the -sv compile
> option to the vlog command.

Well, since all I have at home is the Altera free edition and in fact
it seems it's the only free Modelsim out for Linux right now (well,
Actel has a 45 day trial), I tried these out. Only example complains
about missing support:

Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct  1 2009
-- Compiling module random_test
** Warning: ex2.sv(5): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.

And trying to run it gives:

# vsim random_test      
# Loading sv_std.std
# Loading work.random_test
VSIM 3> run -all
# ** Fatal: ex2.sv(5): Unable to check out verification license for randomize() feature.
#    Time: 0 ps  Iteration: 0  Process: /random_test/#INITIAL#3 File: ex2.sv
# Fatal error in Module random_test at ex2.sv line 5
# 
# HDL call sequence:
# Stopped at ex2.sv 5 Module random_test

But all the others work. Not bad for a freebie...

On Jan 15, 2:40=A0pm, Anssi Saari <a...@sci.fi> wrote:
> Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> writes:
> > You will probably find that quite a few of the SV design features
> > are fully supported in that version - interfaces, always_comb,
> > structs, .* port connection, that sort of thing - but I would
> > be astonished if you had access to any of the big-ticket
> > verification stuff such as classes and randomization. =A0To
> > find out, try these little examples. =A0Be sure to give the
> > files ".sv" extension, or alternatively use the -sv compile
> > option to the vlog command.
>
> Well, since all I have at home is the Altera free edition and in fact
> it seems it's the only free Modelsim out for Linux right now (well,
> Actel has a 45 day trial), I tried these out. Only example complains
> about missing support:
>
> Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct =A01 2009
> -- Compiling module random_test
> ** Warning: ex2.sv(5): (vlog-2186) SystemVerilog testbench feature
> (randomization, coverage or assertion) detected in the design.
> These features are only supported in Questasim.
>
> And trying to run it gives:
>
> # vsim random_test =A0 =A0 =A0
> # Loading sv_std.std
> # Loading work.random_test
> VSIM 3> run -all
> # ** Fatal: ex2.sv(5): Unable to check out verification license for rando=
mize() feature.
> # =A0 =A0Time: 0 ps =A0Iteration: 0 =A0Process: /random_test/#INITIAL#3 F=
ile: ex2.sv
> # Fatal error in Module random_test at ex2.sv line 5
> #
> # HDL call sequence:
> # Stopped at ex2.sv 5 Module random_test
>
> But all the others work. Not bad for a freebie...

Thanks everyone for your input. My question is relating to the cost of
a simulator that supports SystemVerilog Verfication, just how much
should I expect to spend for one license? If its too expensive I'll
have to stick with sytem testbenches.

joe

"jjlindula@hotmail.com" <jjlindula@hotmail.com> writes:

> Thanks everyone for your input. My question is relating to the cost of
> a simulator that supports SystemVerilog Verfication, just how much
> should I expect to spend for one license? If its too expensive I'll
> have to stick with sytem testbenches.

If you have to ask you can't afford it...

Anyway you should check with Mentor, maybe they can give you a deal.
I've never used Questa myself, only Synopsys VCS.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

> Thanks everyone for your input. My question is relating to the cost of
> a simulator that supports SystemVerilog Verfication, just how much
> should I expect to spend for one license? If its too expensive I'll
> have to stick with sytem testbenches.
> 
> joe

To put a ball park on it, about the price of a relatively well-equiped
medium range car ;). If you get a great deal from Aldec / Cadence /
Mentor / Synopsys, maybe the price of a well equiped small car.

On Jan 18, 2:50=A0am, Charles Gardiner <inva...@invalid.invalid> wrote:
> > Thanks everyone for your input. My question is relating to the cost of
> > a simulator that supports SystemVerilog Verfication, just how much
> > should I expect to spend for one license? If its too expensive I'll
> > have to stick with sytem testbenches.
>
> > joe
>
> To put a ball park on it, about the price of a relatively well-equiped
> medium range car ;). If you get a great deal from Aldec / Cadence /
> Mentor / Synopsys, maybe the price of a well equiped small car.

Why is it so expensive?

On Jan 20, 7:46=A0am, "jjlind...@hotmail.com" <jjlind...@hotmail.com>
wrote:
> On Jan 18, 2:50=A0am, Charles Gardiner <inva...@invalid.invalid> wrote:
>
> > > Thanks everyone for your input. My question is relating to the cost o=
f
> > > a simulator that supports SystemVerilog Verfication, just how much
> > > should I expect to spend for one license? If its too expensive I'll
> > > have to stick with sytem testbenches.
>
> > > joe
>
> > To put a ball park on it, about the price of a relatively well-equiped
> > medium range car ;). If you get a great deal from Aldec / Cadence /
> > Mentor / Synopsys, maybe the price of a well equiped small car.
>
> Why is it so expensive?

Not sure!  But I was completely blown away at how much discounts are
offered if you just ask for them... the car analogy really applies
here.  Even better would be a "used car"... i.e. you bargain as if you
are out to buy a used car.  Nevertheless, if you want a cheap tool to
learn Aldec Riviera Pro may be a good deal as well... ofcourse, here
you pay to debug Riviera for Aldec.