VHDL vs Verilog

On Sat, 13 Feb 2010 06:25:13 +0100, whygee wrote:

>The phrase that I partly remember summed up
> many things about the divergences
>between these two major HDL.

It was, and still is, an amusing quote.  Similarly amusing 
is the response, which I think is Janick Bergeron's, to the
question "which HDL do you prefer"; the answer is "the one
I'm not using this week".

VHDL is, by any sensible measure, a hugely superior 
language for RTL design; but it was driven almost
to the point of extinction by Verilog advocates in the
RTL design community, who fell in love with Verilog's 
conciseness and apparent simplicity.  They had some
real ammunition too; Verilog was designed from the 
outset to do a good job of gate-level and netlist
simulation, but VHDL initially lacked some crucial
features to deal with that.  The VITAL standard filled
that gap in VHDL, but its performance has always
lagged far behind what Verilog can do and it's hard
to imagine anyone doing VHDL gate-level simulation
from choice.

The RTL community's reluctance to adopt what it can
from the software world is saddening and mystifying.
I cannot think of even one serious attempt to raise 
the abstraction level of RTL design in the last 
20 years that has been commercially successful.

By contrast, VHDL's limitations in the world of
testbench writing are so severe that it's amazing 
it gained any traction at all in that space.

>> ...to comp.lang.vhdl where you will find polite software people.

>does THAT exist ?

Depends what they have been smoking recently :-)
-- 
Jonathan Bromley

Eric Smith wrote:
> That's a quote by someone who doesn't understand VHDL.
I wrote that it summed up a lot of things,
so it was interesting to me.
I did not infer that it was acurate :-)

yg
-- 
http://ygdes.com / http://yasep.org

Petter Gustad wrote:
> whygee <yg@yg.yg> writes:
>> Does anybody know the exact wording and origin ?
> You mean this?
> http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4
yes, that's it !

thanks,
> Petter
yg

-- 
http://ygdes.com / http://yasep.org

Jonathan Bromley wrote:
> On Sat, 13 Feb 2010 06:29:20 +0100, whygee wrote:
>> I did not know that I would trigger so many strong reactions,
> <wipes spilt coffee from keyboard, resets cardiac pacemaker>
> Ignorance is bliss, but often unhelpful.
sorry for your keyboard :-)
yg
-- 
http://ygdes.com / http://yasep.org

Hi !

Jonathan Bromley wrote:
> On Sat, 13 Feb 2010 06:25:13 +0100, whygee wrote:
>> The phrase that I partly remember summed up
>> many things about the divergences
>> between these two major HDL.
> It was, and still is, an amusing quote.
you get the point of the intention for the quote :-)

>  Similarly amusing 
> is the response, which I think is Janick Bergeron's, to the
> question "which HDL do you prefer"; the answer is "the one
> I'm not using this week".
Funny, I have tried to reinvent quite a lot of wheels,
but never a HDL.

> VHDL is, by any sensible measure, a hugely superior 
> language for RTL design; but it was driven almost
> to the point of extinction by Verilog advocates in the
> RTL design community, who fell in love with Verilog's 
> conciseness and apparent simplicity.
Well, I learnt VHDL because :
  - I'm french and it's a de facto HDL in Europe
     (or at least it was 10 years ago)
  - it's very rich and expressive,
     and I discover something new all the time

but yes, the overhead of learning all the subtleties
can distract my efforts away from actual design.
But I stick to it.
Fortunately, I don't run (yet) an ASIC design company :-D

>  They had some
> real ammunition too; Verilog was designed from the 
> outset to do a good job of gate-level and netlist
> simulation, but VHDL initially lacked some crucial
> features to deal with that.
I thought that VHDL was initially designed for simulation,
before synthesisers used it too (?)

>  The VITAL standard filled
> that gap in VHDL, but its performance has always
> lagged far behind what Verilog can do and it's hard
> to imagine anyone doing VHDL gate-level simulation
> from choice.
hmmm... interesting, I have never thought about this.
Do you refer to post-route simulations here ?
And, according to your experience,
why would it be so slow compared the Verilog ?

> The RTL community's reluctance to adopt what it can
> from the software world is saddening and mystifying.
> I cannot think of even one serious attempt to raise 
> the abstraction level of RTL design in the last 
> 20 years that has been commercially successful.
I think that I'll leave this aspect uncovered in
my paper :-)

> By contrast, VHDL's limitations in the world of
> testbench writing are so severe that it's amazing 
> it gained any traction at all in that space.
what are these limitations, in your opinion ?
I don't think I have run into any yet.

thanks for your explanations,

yg
-- 
http://ygdes.com / http://yasep.org

John_H wrote:

> The quote predates Oct 200 as noted by the post:
> http://www.fpga-faq.com/archives/26475.html#26480
i think that you missed one zero :-)

But I'm surprised that the title of this post
is exactly the same as mine. Damnit, I want
to be original and I write the same stuff as others again :-/

> Elsewhere the quote is attributed to David Bishop (in a few places
> including a 2007 conference paper) but I'm not certain if that's from
> a restatement (e.g. January 2006) or the original from Y2K or before.
> David Bishop has at least reused the quote in 2006 prior to the 2007
> reference.
Does he like to "quote and paste" ? :-D

thanks for the hints and pointers :-)

yg
-- 
http://ygdes.com / http://yasep.org

On Feb 13, 4:20=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Sat, 13 Feb 2010 10:15:34 +0100, Petter Gustad
>
> <newsmailco...@gustad.com> wrote:
> >whygee <y...@yg.yg> writes:
>
> >> Does anybody know the exact wording and origin ?
>
> >You mean this?
>
> >http://groups.google.com/group/comp.lang.vhdl/msg/c9edc45f3a7c86d4
>
> Right, that's it, but the epithet has been around far
> longer than that post.

The quote predates Oct 200 as noted by the post:
http://www.fpga-faq.com/archives/26475.html#26480

Elsewhere the quote is attributed to David Bishop (in a few places
including a 2007 conference paper) but I'm not certain if that's from
a restatement (e.g. January 2006) or the original from Y2K or before.
David Bishop has at least reused the quote in 2006 prior to the 2007
reference.

whygee <yg@yg.yg> wrote:

>hi,
>
>recently I read a quote about VHDL vs Verilog,
>along the lines of "VHDL is made by SW people who
>don't understand HW and vice versa"...

Bottom line is that VHDL is more powerful & complicated than Verilog
but neither are the perfect language. For people with a background in
schematic capture for FPGA design VHDL may be a big step to take.
Verilog looks just like a netlist which is much closer the schematic
capture.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

On 2/13/2010 5:25 AM, whygee wrote:

> thanks for the off-topic anyway :-)
>
> yg

...and thank you for taking it in the spirit it was intended! :-)
All the best, Symon.

>
> The RTL community's reluctance to adopt what it can
> from the software world is saddening and mystifying.
> I cannot think of even one serious attempt to raise
> the abstraction level of RTL design in the last
> 20 years that has been commercially successful.
>

But RTL generally is very different to software, because RTL has the
extra requirement that things have to happen at explicit times. I'm
not sure RTL could adopt much from the software world that would make
RTL quicker/easier.

I can't think of how OO methods would work for RTL coding. For
testbenches maybe. Although procedural testbenches are probably more
than adequate for the majority of cases.

Dynamic types of course are also no good for RTL, because signals/
variables are static. Dynamic languages could be used for testbenches
but then dynamic languages are slower, possibly not what you want for
testbenches. Although I guess the speed impact of a dynamic language
for testbenches would depend on the relative complexity of a testbench
to the RTL design.

Agile methods are probably out. Apparently they're good for quickly
changing code to accommodate quickly changing requirements. But
because RTL coding is harder than writing software (because of the
extra requirement that things have to happen happen at specific
times), quickly changing RTL code isn't really possible. And for FPGA
designs tying specs down to a reasonable level is a lot easier than
for software engineering, because an FPGA has at least well defined
requirements in what it has to drive on a circuit board. So just write
the specs right, or mostly right to start with, and you don't need
agile.

I can't think of how any recent software methods would help RTL. Maybe
I'm a stick-in-the-mud :-)

> By contrast, VHDL's limitations in the world of
> testbench writing are so severe that it's amazing
> it gained any traction at all in that space.

(1) vhdl is used for RTL so use the same language for testbenches,
and

(2) a lot of electronics engineers' requirements for test benches are
pretty simple, and so VHDL is mostly adequate; i.e. basic test-
benching, then debug on hardware, maybe also using something like
chipscope.

Writing good testbenches, especially self-checking ones, takes time.
And you have to debug the testbenches as well as the RTL. So if you
can debug the RTL in hardware, why spend a lot of time writing/
debugging testbenches?

The reason why I say 'suspect' above is because I don't really know,
but the majority of electronics engineers who design FPGAs that I've
come across whilst working as an electronics engineer, do the minimum
amount of testbenching, with self-cheking testbenches very thin on the
ground.

I'm supposing that full time ASIC/FPGA designers (rather than
electronics engineers who design hardware as well as designing FPGAs)
do put a lot of effort into writing good testbenches, but then they'll
probably be using SystemVerilog or something similar.

It would be interesting to see some statistics on debug methods
actually used in industry.

Of course you could say that if VHDL was easier to use for writing
testbenches more electronics engineers would be writing more
comprehensive testbenches, hmmm...

It would be nice if VHDL had a more flexible approach to creating/
controlling processes (or threads or tasks, whatever they might be
called). VHDL static processes are fine for RTL of course, but
essentially a bit crumby for testbenches. It will be interesting to
see what future vhdl standards throw up. I would like some process/
thread/task control in VHDL, much more than OO additions.