VHDL vs Verilog

Petter Gustad <newsmailcomp6@gustad.com> wrote:

>nico@puntnl.niks (Nico Coesel) writes:
>
>> Bottom line is that VHDL is more powerful & complicated than Verilog
>> but neither are the perfect language. For people with a background in
>
>Depends upon which Verilog standard you refer to as Verilog. IEEE-1800
>is way more powerful than any of the VHDL standards IMHO.

I'm talking about the Verilog you can actually use with todays tools.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

On 14 Feb, 16:02, Petter Gustad <newsmailco...@gustad.com> wrote:

> > driven development. For VHDL, unit tests would mean I would have to
> > write self-checking testbenches, and unfortunately I don't tend to get
> > the time for that. It would be nice however to have a unit test
>
> How do you have time *not* to do that :-)

Because I write stimulus only test benches. Which of course only means
visual inspection of results. That method I find is the quickest way
of getting to a working FPGA design.

How do you get the time to do self-checking testbenches? :-)

Paul.

On Feb 14, 11:13=A0am, Paul <pault...@googlemail.com> wrote:
> On 14 Feb, 16:02, Petter Gustad <newsmailco...@gustad.com> wrote:
>
> > > driven development. For VHDL, unit tests would mean I would have to
> > > write self-checking testbenches, and unfortunately I don't tend to ge=
t
> > > the time for that. It would be nice however to have a unit test
>
> > How do you have time *not* to do that :-)
>
> Because I write stimulus only test benches. Which of course only means
> visual inspection of results. That method I find is the quickest way
> of getting to a working FPGA design.
>
> How do you get the time to do self-checking testbenches? :-)
>
> Paul.

I tend to use self-checking test benches.  There is some question as
to what is best, but I find that often my design has to be tweaked
after I have it working and once I have the test bench working, the
tweaked design can be tested very easily.  I guess it is a question of
whether the test bench is a one time thing or will be "reused".  I
often find I "reuse" my test benches in both ways, I often run them
more than once and I use parts of one test bench in others as I test
my way up the integration process.

Oh, also, there has been more than once that my test bench was
actually another FPGA design that ended up on a test fixture to
production test the real board.  That can be a fair amount of work,
but not as much work as separately testing two FPGA designs.

Rick

On 14 Feb, 17:15, rickman <gnu...@gmail.com> wrote:
>
> I tend to use self-checking test benches. =A0There is some question as
> to what is best, but I find that often my design has to be tweaked
> after I have it working and once I have the test bench working, the
> tweaked design can be tested very easily. =A0I guess it is a question of
> whether the test bench is a one time thing or will be "reused". =A0I
> often find I "reuse" my test benches in both ways, I often run them
> more than once and I use parts of one test bench in others as I test
> my way up the integration process.
>
> Oh, also, there has been more than once that my test bench was
> actually another FPGA design that ended up on a test fixture to
> production test the real board. =A0That can be a fair amount of work,
> but not as much work as separately testing two FPGA designs.
>
> Rick

I thought non-checking test benches was the most prevalent method
used, because that's what I do and almost all engineers I've come
across do as well. Hmmmm...... maybe I need to change my mind :-)

nico@puntnl.niks (Nico Coesel) writes:

> Petter Gustad <newsmailcomp6@gustad.com> wrote:
>
>>nico@puntnl.niks (Nico Coesel) writes:
>>
>>> Bottom line is that VHDL is more powerful & complicated than Verilog
>>> but neither are the perfect language. For people with a background in
>>
>>Depends upon which Verilog standard you refer to as Verilog. IEEE-1800
>>is way more powerful than any of the VHDL standards IMHO.
>
> I'm talking about the Verilog you can actually use with todays tools.

I actually used IEEE-1800 several years ago (VCS and DC). Today it's
supported by even more tools, including Quartus.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Paul <pault.eg@googlemail.com> writes:

> visual inspection of results. That method I find is the quickest way
> of getting to a working FPGA design.

Visual inspection does not scale. If you run the test more a couple
times you have probably saved the time it takes to write the
self-checking test bench.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Paul <pault.eg@googlemail.com> writes:

> I do use unit tests on occasion for software, but I don't use test
> driven development. For VHDL, unit tests would mean I would have to
> write self-checking testbenches, and unfortunately I don't tend to get
> the time for that. It would be nice however to have a unit test
> environment for VHDL. One day I might get the time to use it....

I usually don't have time to *not* write a self-checking testbench :)

And on the occasions I think I'll get away without it, I often end up
writing one anyway!

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

On Feb 14, 12:41=A0pm, Paul <pault...@googlemail.com> wrote:
> On 14 Feb, 17:15, rickman <gnu...@gmail.com> wrote:
>
>
>
>
>
> > I tend to use self-checking test benches. =A0There is some question as
> > to what is best, but I find that often my design has to be tweaked
> > after I have it working and once I have the test bench working, the
> > tweaked design can be tested very easily. =A0I guess it is a question o=
f
> > whether the test bench is a one time thing or will be "reused". =A0I
> > often find I "reuse" my test benches in both ways, I often run them
> > more than once and I use parts of one test bench in others as I test
> > my way up the integration process.
>
> > Oh, also, there has been more than once that my test bench was
> > actually another FPGA design that ended up on a test fixture to
> > production test the real board. =A0That can be a fair amount of work,
> > but not as much work as separately testing two FPGA designs.
>
> > Rick
>
> I thought non-checking test benches was the most prevalent method
> used, because that's what I do and almost all engineers I've come
> across do as well. Hmmmm...... maybe I need to change my mind :-)

I can't say I have worked with that many engineers well enough to know
how their test benches work, but I can only think of one designer (I
hate to call him an engineer even if he has a degree) who does not use
self-checking test benches.  But then this guy also doesn't use static
timing analysis.  He claims a post-route simulation will find timing
errors.  I actually could not get him to understand why everyone else
uses static timing analysis and why the vendors put so much effort
into providing the tool!

Rick

>hi,
>
>recently I read a quote about VHDL vs Verilog,
>along the lines of "VHDL is made by SW people who
>don't understand HW and vice versa"...
>
>Does anybody know the exact wording and origin ?
>
>yg
>-- 
>http://ygdes.com / http://yasep.org
>

One can see example between VHDL and verilog in the following example. I
developed sparse memory model in each language. While I could do it easily
in VHDL in verilog I needed VPI (c - interface).
The work was posted on :
h===://bknpk.no-ip.biz/my_web/MiscellaneousHW//memory_hdl_models.html	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com