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Modelsim PE vs. Aldec Active-HDL (PE)

Started by Pete Fraser March 3, 2010
rickman <gnuarm@gmail.com> writes:

> Ok, that's what I get from the Aldec or Lattice ispLever tools. I'll > have to look at EMACs sometime soon. Can it be used to do pretty > print formatting on VHDL files?
Yes, it will "beautify", either the entire buffer or the current region (using C-c C-b or C-c M-b). I'm also using Emacs/Gnus writing this message and reading this newsgroup. I'm using Emacs/Mew for writing E-mail, also writing Verilog, Common Lisp, Python, C, Java, LaTex, etc., as well as doing GIT commits, diffs, creating branches, merges, even surfing the web using w3m. Dired in Emacs provides a great file browser where I can to bulk editing etc. Whenever I want to perform tedious repetitive editing tasks I will usually make a small Emacs Lisp function to do it for me... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
rickman <gnuarm@gmail.com> writes:

> On Mar 8, 6:53&#4294967295;am, Martin Thompson <martin.j.thomp...@trw.com> wrote: >> rickman <gnu...@gmail.com> writes: >> > I find the GUI will save me a lot of typing when instantiating >> > modules. &#4294967295;I use the "generate test bench" feature to build a file >> > with the meat and potatoes in it and I copy that to the higher level >> > module. >> >> Ahh, I use VHDL-mode in Emacs for that, which is why I haven't missed >> it :) > > Are you saying that Emacs understands VHDL well enough to build a test > bench for you? Will it also build a component declaration or > instantiation automatically? These three things could be automated, > but I have never taken the time to do it. Making it part of the > editor makes perfect sense.
Here's an example: Given this (for which I typed very few letters due to autocompletion and other magic): entity example is generic ( blah : integer := 5); port ( clk : in std_logic; reset : in std_logic; a : in integer; b : out integer); end entity example; I can "copy-port" and "paste as testbench" to get this (I have done nothing further to it at all): < being vhdl paste > library ieee; use ieee.std_logic_1164.all; ---------------------------------------------------------------------------------------------------------------------------------- entity tb_example is end entity tb_example; ---------------------------------------------------------------------------------------------------------------------------------- architecture test of tb_example is -- component generics constant blah : integer := 5; -- component ports signal clk : std_logic; signal reset : std_logic; signal a : integer; signal b : integer; -- clock signal Clk : std_logic := '1'; -- finished? signal finished : std_logic; begin -- architecture test -- component instantiation DUT: entity work.example generic map ( blah => blah) port map ( clk => clk, reset => reset, a => a, b => b); -- clock generation Clk <= not Clk after 10 ns when finished /= '1' else '0'; -- waveform generation WaveGen_Proc: process begin finished <= '0'; -- insert signal assignments here finished <= '1'; report (time'image(now) & " Finished"); wait; end process WaveGen_Proc; end architecture test; ---------------------------------------------------------------------------------------------------------------------------------- configuration tb_example_test_cfg of tb_example is for test end for; end tb_example_test_cfg; ---------------------------------------------------------------------------------------------------------------------------------- < end vhdl paste > I still need to update the vhdl-mode config so that clk doesn't get defined twice - I broke that at some point, and haven't gone back to fix it properly, I just delete the line. That feels very lazy, now I'm admitting it :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
> Are you saying that Emacs understands VHDL well enough to build a test > bench for you? Will it also build a component declaration or > instantiation automatically? These three things could be automated, > but I have never taken the time to do it. Making it part of the > editor makes perfect sense.
The problem with emacs is you need three knuckles in each finger to drive it. The following perl script builds a basic testbench from a *.vhd entity. http://www.nialstewartdevelopments.co.uk/download/tb_gen.pl It's not perfect (generics throw it I think, I keep meaning to fix that) but it's saved me a lot of time. Nial.
On Mar 9, 4:37=A0am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> > Are you saying that Emacs understands VHDL well enough to build a test > > bench for you? =A0Will it also build a component declaration or > > instantiation automatically? =A0These three things could be automated, > > but I have never taken the time to do it. =A0Making it part of the > > editor makes perfect sense. > > The problem with emacs is you need three knuckles in each finger to > drive it.
Remap the caps-lock key to CTRL and you're back to only two knuckles :) -a
On Mar 8, 4:38=A0pm, rickman <gnu...@gmail.com> wrote:
> On Mar 8, 4:40=A0pm, Andy Peters <goo...@latke.net> wrote: > > > > > On Mar 8, 1:32=A0pm, rickman <gnu...@gmail.com> wrote: > > > > On Mar 8, 6:53=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrot=
e:
> > > > > rickman <gnu...@gmail.com> writes: > > > > > I find the GUI will save me a lot of typing when instantiating > > > > > modules. =A0I use the "generate test bench" feature to build a fi=
le
> > > > > with the meat and potatoes in it and I copy that to the higher le=
vel
> > > > > module. > > > > > Ahh, I use VHDL-mode in Emacs for that, which is why I haven't miss=
ed
> > > > it :) > > > > Are you saying that Emacs understands VHDL well enough to build a tes=
t
> > > bench for you? > > > It will create a skeleton for you. > > > >=A0Will it also build a component declaration or > > > instantiation automatically? =A0These three things could be automated=
,
> > > but I have never taken the time to do it. =A0Making it part of the > > > editor makes perfect sense. > > > The skeleton has a nice header, an instance of the DUT, signal > > declarations for all DUT I/O and a simple clock generator. Of course > > you have to create your own stimulus and add instantiations of other > > models as necessary. > > Ok, that's what I get from the Aldec or Lattice ispLever tools. =A0I'll > have to look at EMACs sometime soon. =A0Can it be used to do pretty > print formatting on VHDL files?
Yep, it beautifies buffers beautifully. The comprehensive auto-complete feature is the best reason to use emacs and its vhdl-mode. Type pr then <tab> and blam, it inserts a process template, which you can customize with clock name, reset name and type (async/sync) and polarity, and it'll ask for a process label too. Really, I don't know how anyone does any VHDL coding without it. -a
On Mar 8, 1:34=A0pm, rickman <gnu...@gmail.com> wrote:
> On Mar 8, 7:04=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > KJ <kkjenni...@sbcglobal.net> writes: > > > I guess that's a point in its favour (assuming I can't "convert" the > > incomers to Emacs :) > > You can convert me. =A0I just need to know that it is an advantage to > switch.
As the old commercial went, "Try it, you'll like it!" -a
On Mar 9, 3:17=A0am, Petter Gustad <newsmailco...@gustad.com> wrote:
> rickman <gnu...@gmail.com> writes: > > Ok, that's what I get from the Aldec or Lattice ispLever tools. =A0I'll > > have to look at EMACs sometime soon. =A0Can it be used to do pretty > > print formatting on VHDL files? > > Yes, it will "beautify", either the entire buffer or the current > region (using C-c C-b or C-c M-b). > > I'm also using Emacs/Gnus writing this message and reading this > newsgroup. I'm using Emacs/Mew for writing E-mail, also writing > Verilog, Common Lisp, Python, C, Java, LaTex, etc., as well as doing > GIT commits, diffs, creating branches, merges, even surfing the web > using w3m. Dired in Emacs provides a great file browser where I can to > bulk editing etc. Whenever I want to perform tedious repetitive > editing tasks I will usually make a small Emacs Lisp function to do it > for me... > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?
Petter, There was a guy in some of the Yahoo groups who had a tag line about not being able to chew a radio wave. For some reason it struck me as annoying and eventually I asked him to change it. He was not wedded to it and was nice enough to do so. I find your tag line to be pretty annoying as well. It is one of those things that once you've read it, you don't need to keep reading it. But it is there at the bottom of each post you make and it is hard to ignore. At least I find it hard to ignore. What are the chances you can switch to something else? Rick
In comp.arch.fpga rickman <gnuarm@gmail.com> wrote:

(snip, someone wrote)

>> A: Because it messes up the order in which people normally read text. >> Q: Why is top-posting such a bad thing? >> A: Top-posting. >> Q: What is the most annoying thing on usenet and in e-mail?
(snip, someone else wrote)
> I find your tag line to be pretty annoying as well. It is one of > those things that once you've read it, you don't need to keep reading > it. But it is there at the bottom of each post you make and it is > hard to ignore. At least I find it hard to ignore. What are the > chances you can switch to something else?
I agree. While I mostly agree that top posting is bad, I don't believe that it is always true. I will rarely read a post if there is nothing new in the first two pages scrolling down. If I do get to the bottom, though, I do seem to keep reading the above comments. In the case of a small addition to a large post, and which has no likely follow-ups. (Doesn't ask a question or extend one.) I would rather see it at the top where I can read it quickly. I don't mind the comments applied to actual top posts, but it gets pretty annoying to see it all the time. -- glen
rickman <gnuarm@gmail.com> writes:

> I find your tag line to be pretty annoying as well. It is one of
Of course I can remove it. I just got a little curious. Is it that I've been using it for so long? Is it the length? Or is it the context that annoys you?
> It is one of those things that once you've read it, you don't need to > keep reading it.
There are other readers here besides you. There's probably new people entering the group every day. The sig was mostly targeted towards new participants.
> But it is there at the bottom of each post you make and
That's the case with most sigs.
> hard to ignore. At least I find it hard to ignore. What are the > chances you can switch to something else?
This will have to do until I dig out some of my older ones... Petter -- .sig removed by request.
On Mar 21, 3:43=A0pm, Petter Gustad <newsmailco...@gustad.com> wrote:
> rickman <gnu...@gmail.com> writes: > > I find your tag line to be pretty annoying as well. =A0It is one of > > Of course I can remove it. I just got a little curious. Is it that > I've been using it for so long? Is it the length? Or is it the context > that annoys you?
It is just the repetition of the message I think. First, I guess I don't agree that it is something that needs to be addressed in this way. Others have used this sort of sig too and after some several hundreds or thousands of times of seeing it it becomes an annoyance. The same is true for commercials on TV. I can't stand some of them the first time I see them. Others start getting on my nerves after a few dozen times. That is why I use the mute and it is also why I haven't done anything to get more channels after I fell of the digital cliff on the broadcast conversion. I now get three channels from one public TV station and am pretty happy with that actually. Thanks for being understanding about your sig. Rick