Can a glitch-free mux be designed in an FPGA?

On Tuesday, May 29, 2018 at 7:50:51 AM UTC-4, Thing241 wrote:
> > Actually, there is no reason for a LUT to glitch where logic wouldn't
> 
> I agree, based on the structure of the N-input LUT (2^N flops feeding N levels of glitchless muxes).  But Xilinx won't admit it.  The official line from Xilinx is that a single input change won't glitch the output (which covers the 2-input mux case in question), but multiple inputs changing might glitch.  After looking into the LUT structure I have concluded that any collection of inputs that cannot change the output cannot glitch the output, but again, Xilinx won't confirm this.

I'm not sure you can say this.  No, that's wrong.  I *am* sure you *can't* say this.  

The LUTs in most FPGAs are specifically constructed to prevent changing a single control signal causing a glitch.  This is possible because the control signals drive 2 input muxes made of a pair of transmission gates.  They are constructed so the turn on time is always longer than the turn off time.  This leaves the output node in a high impedance allowing the capacitance to hold the previous value until the new value is driven by the other gate in the pair.  

When more than one control signal is changing, the state of different pairs of transmission gates which have not been designed to match can not be guaranteed to be switching in the same manner.  The glitchless behavior comes from careful design at a low level.  It would appear this glitchless behavior is too hard to create across the entire LUT. 

But maybe I don't understand you premise.  I am assuming we are talking about something like A & ~C | B & C with both A and C changing at the same time.  C goes from 1 to zero and A goes from 0 to 1 while B stays at 1.  In this case the output depends on the relative speeds withing the LUT.  Maybe you are talking about something like A | B | C where A and B transition while C is always a 1?  I am pretty sure in this case there would be no glitch since there are no intermediate states that will output a 0. 

Rick C.

> Maybe you are talking about something like A | B | C where A and B transition while C is always a 1?  I am pretty sure in this case there would be no glitch since there are no intermediate states that will output a 0. 
> 
Exactly.  LUTs don't glitch "where logic wouldn't" (as rickman said).
In a recent exchange with a Xilinx engineer on one of their forums I proposed that if a LUT were implementing an AND gate, and one of the inputs was low, the other inputs could not glitch the output regardless of how they switched (collectively).  He would not agree, again quoting the Xilinx mantra that only "single" inputs are guaranteed not to cause a glitch.

On Wednesday, May 30, 2018 at 5:54:51 AM UTC-4, thing241 wrote:
> > Maybe you are talking about something like A | B | C where A and B transition while C is always a 1?  I am pretty sure in this case there would be no glitch since there are no intermediate states that will output a 0. 
> > 
> Exactly.  LUTs don't glitch "where logic wouldn't" (as rickman said).
> In a recent exchange with a Xilinx engineer on one of their forums I proposed that if a LUT were implementing an AND gate, and one of the inputs was low, the other inputs could not glitch the output regardless of how they switched (collectively).  He would not agree, again quoting the Xilinx mantra that only "single" inputs are guaranteed not to cause a glitch.

There is what the chip will do and what the company guarantees...  Sort of a Forest Gump distinction I think.  Box of chocolates and all that... 

Rick C.

onsdag den 30. maj 2018 kl. 11.54.51 UTC+2 skrev thing241:
> > Maybe you are talking about something like A | B | C where A and B transition while C is always a 1?  I am pretty sure in this case there would be no glitch since there are no intermediate states that will output a 0. 
> > 
> Exactly.  LUTs don't glitch "where logic wouldn't" (as rickman said).
> In a recent exchange with a Xilinx engineer on one of their forums I proposed that if a LUT were implementing an AND gate, and one of the inputs was low, the other inputs could not glitch the output regardless of how they switched (collectively).  He would not agree, again quoting the Xilinx mantra that only "single" inputs are guaranteed not to cause a glitch.

looks like the late Peter Alfke agreed

https://www.fpgarelated.com/showthread/comp.arch.fpga/32950-1.php

On Wednesday, May 30, 2018 at 3:42:41 PM UTC-4, lasselangwad...@gmail.com wrote:
> 
> looks like the late Peter Alfke agreed
> 
> https://www.fpgarelated.com/showthread/comp.arch.fpga/32950-1.php

Thanks for the link.  I have never seen that claim made by a Xilinx rep before.