(@Echoonezero)
Hello adouville,There are s_WRN and s_RDN signals being sent to DUT and hence I realised I can use these signals in a proper way to decide read and write operation.Currently,...
Update: I could find a way to read real values. Just created a real variable and multiplied it with 1 ns and assigned it to time variable.ex: variable a: time;variable...
Hello adouville,Sorry for not posting the complete testbench. I thought the logic implemented in the process would be sufficient to convey the information. The below...
Hello,I am a newbie in verifying complex FPGA designs. In my testbench, I am reading the test vectors from a text file and assigning them to the input ports...
Hello,I have the following questions:1. A Quartus Prime Lite version is sufficient for my FPGA design. Can I use only the Lite version in my company for commercial...
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