Hello,

I am a newbie in verifying complex FPGA designs.  In my testbench, I am reading the test vectors from  a text file and assigning them to the input ports of my FPGA design. Thats when I find the above error while reading the first line of my text file. Sample data in text file, error log and my testbench code are in the attached file.

Please let me know if something is not clear in my explanation, and guide me to solve the error.

Modelsim_error.txt

Thank you!

Hello,

Do you remove something in the testbench you enclosed? Because the actual code is a bit strange: no entity, no architecture, ...

I suggest you to look at a VHDL handbook if this is the exact code!

Moreover, why are the first errors focused on your test pattern? Do you compile it?

If you add an entity, plus an architecture plus the library to the test bench, it should be OK.

Hello adouville,

Sorry for not posting the complete testbench. I thought the logic implemented in the process would be sufficient to convey the information. The below attachment has the complete testbench.

Also, I found out that the error was due to not reading the first data (time value) from the text file in the right manner. After removing the time values from the text file, I could see that the simulation started and test vectors were assigned to the input ports. I have the below questions:

1. How do I read the real value data ex: 206.3, 209.8, 210.2 etc from a text file in my testbench?

2. How do I drive the bidirectional data bus in my testbench? I have tried this in line 151 of the attachment. Let me know if this is correct:

s_AD <= s_AD_temp when s_E = '1' else (others => 'Z');

modelsim_errror.txt

Thank you very much in advance!

Update: I could find a way to read real values. Just created a real variable and multiplied it with 1 ns and assigned it to time variable.

ex: variable a: time;

variable b: real;

read(<line_variable>, b)

a = b * 1 ns;

So now I only need answers to the second question. I am not able to drive the bidirectional signal the right way. The contention is between the testbench writing the test vectors to the bidirectional bus and the DUT writing back the results on the same bus.

Thank you very much in advance!

The code in your second question seems to be ok.

The only question is how your DUT knows a data is writing to it by the test bench as the 's_E' is not an input to the DUT. Which is the master?

Hello adouville,

There are s_WRN and s_RDN signals being sent to DUT and hence I realised I can use these signals in a proper way to decide read and write operation.

Currently, I have deleted the signal s_E and the variable v_E and wrote something like this outside the process:

s_AD <= s_AD_temp when s_WRN = '0' else 

(others => 'Z') when s_RDN = '0' else

s_AD;

So, I am writing s_AD_temp to s_AD when S_WRN is enabled, driving s_AD to "Z" when the DUT has to perform write operation or else s_AD is same as it is.