Gene Breniman (@genebren)

Gene Breniman has over 30 years experience in design and development of hardware and software for embedded systems. He has worked in a variety of fields, including avionics, life sciences and automatic test equipment engineering.

VHDL tutorial - A practical example - part 3 - VHDL testbench

Gene Breniman ● June 25, 2011●8 comments

Gene Breniman walks a complete VHDL testbench workflow for a CPLD-based data acquisition engine, from Xilinx ISE testbench generation to stimulus processes. He shows clock and SPI gating, a simulated ADC data generator tied to ADC_LRCK and ADC_BCK, and how simulation revealed a timing bug in the nvSRAM header that was then fixed in the VHDL. Practical and hands-on for verification work.

VHDL tutorial - A practical example - part 2 - VHDL coding

Gene Breniman ● May 27, 2011

Gene Breniman walks through the VHDL coding for a CPLD-based data acquisition engine, turning the hardware spec into a working state machine and signal generators. The article explains SPI and I2S timing choices, an internal SPI peripheral latch, and counter-based timing (seqCount and CycleCnt) used to create LRCK, BCK, SPI SCK and nvSRAM write control. It’s a practical, implementation-focused guide for embedded designers.

VHDL tutorial - A practical example - part 1 - Hardware

Gene Breniman ● May 18, 2011●1 comment

Gene Breniman walks through a practical CPLD-based data acquisition engine built for a low-power handheld instrument, focusing on hardware choices, signal flow, and pin assignments. The article explains component selection including a PCM1870 ADC, CY14B101Q2 serial nvSRAM, and an XC2C64A CPLD, and shows how the CPLD acts as an SPI sequencer and I2S clock master while minimizing microcontroller pins and power draw.

VHDL tutorial - Creating a hierarchical design

Gene Breniman ● May 22, 2008●6 comments

Complex VHDL files quickly become hard to read and maintain. This tutorial demonstrates how to break a design into reusable entities by building a divide-by-10 component, explaining ports, sensitivity lists, and the inout usage for a toggled output. It then shows how to instantiate and chain three instances into a ÷1000 divider, with synthesis notes from compiling to an XC2C128 device.

VHDL tutorial - combining clocked and sequential logic

Gene Breniman ● March 3, 2008

Need the ADC clock to sometimes be the raw 40MHz input? Gene Breniman shows how to extend a reloadable, counter-based VHDL clock divider to support a master-clock pass-through by using a conditional signal assignment to switch between the internal ADCClk and Mclk. The article also covers remapping ClkSel values and includes a working XC2C32A CPLD build that leaves room for future enhancements.

VHDL tutorial - part 2 - Testbench

Gene Breniman ● October 30, 2007●3 comments

In this follow-up Gene Breniman builds a VHDL testbench in Xilinx ISE, showing how to generate a continuous master clock, apply a power-on reset, and sequence register strobes to change clock divisors. He walks through timing waits and observation delays needed to verify ADC clock rates. The article also shows how simulation exposed a copy-paste bug in the original design.

VHDL tutorial

Gene Breniman ● October 4, 2007●9 comments

Gene Breniman presents a hands-on VHDL walkthrough for a programmable clock divider implemented on a Xilinx CoolRunner CPLD (XC2C32A). The example shows how to declare ports and internal signals, implement a clock-division process with reset and falling-edge detection, and create a simple addressable latch to select clock rates from a 40MHz master clock. It’s a compact, practical guide for embedded engineers learning VHDL and CPLD design.

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