An absolute position encoder VHDL core

Fabien Le Mentec November 11, 2015
Introduction

Let's consider motorized systems controlled by electronics. A closed loop architecture looks like this:

The following components are involved:

  • the motor itself (DC, stepper ...),
  • the controller, in charge of computing position according to the whole system state,
  • the driver board in charge of generating signals and power for the motor,
  • the position encoder, the subject of this post.

Most of the time, there is a difference between the position the system...


I don’t often convert VHDL to Verilog but when I do ...

Christopher Felton December 24, 20142 comments
VHDL to Verilog

I don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement).  For the most part I am HDL agnostic.  Well that is not true, I have a strong preference for MyHDL, and an insubstantial preference for VHDL over Verilog.  The choice of HDL for a project is often complicated, irrational, sometimes rational, but most often random.  It is often not a choice of the developer - for...


Point of View

Christopher Felton August 29, 20146 comments

I was caught of guard when someone commented:

"when a FIR filter is full of multiple loops and complex code, something is wrong"

The comment was made during an informal discussion on alternative hardware description languages (HDL) and was targeted to the straightforward FIR filter implemented in MyHDL

(different FIR description simulation results) 

Personally, (and...


MyHDL Presentation Examples

Christopher Felton August 26, 2014

The last two years I presented at EELive.  The first year as an overview of MyHDL and a strong case why you should be using MyHDL as your hardware description language (HDL) [paper].  The second year was an introduction to three alternative HDLs (alt.hdl), including MyHDL.  I also presented at a regional Python conferene: pyohio.  At the Python conference I presented...


Little to no benefit from C based HLS

Christopher Felton April 5, 2014

Last updated 07-Nov-2015

As I write this I am on a plane and my destination is EELive 2014 where I am going to give a talk hardware design: the grunge era.  It is a shotgun introduction to three alternative hardware description languages (alt.hdl). The three languages briefly introduced in the talk are: bsv, chisel, and myhdl.  The goal of the talk is simply to raise awareness of the three...


MyHDL Interface Example

Christopher Felton January 19, 20142 comments
MyHDL Interfaces Example

With the next release of MyHDL, version 0.9, conversion of interfaces will be supported.  In this context an interface is any object with a Signal attribute.  This can be used to simplify connection between modules and port definitions.  For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:

class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...

MyHDL @EDAPlayground

Christopher Felton October 24, 2013

Trying out MyHDL became a little easier recently.  MyHDL is now avaialbe @EDAPlayground.  One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL.

The @EDAPlayground has two main panels. On the left is the testbench and the right the HDL description to be tested.

There are a couple examples...


Introducing the VPCIe framework

Fabien Le Mentec August 31, 20133 comments
Introduction

My daily work involves platforms featuring an embedded CPU communcating with a FPGA device over a PCI Express link (PCIe for short). The main purpose of this link is for the CPU to convey configuration, control, and status commands to hardware slaves implemented in the FPGA. For data intensive applications (2D XRay detector readout backend), this link can also be used as a DMA channel to transfer data from the FPGA to the CPU memory. Finally, a slave can interrupt the CPU using...


Learning VHDL - Basics

Enrico Garante June 15, 20135 comments

Since FPGA are becoming more accessible to the hobbyist, learning how to use them can be really useful for certain applications, like DSP and video generation; moreover, engineers that are able to code in VHDL/Verilog are always requested on the job market.

In this tutorial I will cover the basics of Xilinx ISE and VHDL. I willl base my code on the Basys2 board from Digilent: it is really cheap (especially for students) and has a lot of features on board, as you can see from the picture...


MyHDL ... MyPWM

Christopher Felton June 4, 2013

The PWM topic appears to be popular lately on the fpgarelated site.  This is coincidence, but I typically find the topic of modulating and demodulating signals interesting.  For digital systems it is always entertaining to play with PWMs.  The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin.  The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).  

As...


MyHDL FPGA Tutorial I (LED Strobe)

Christopher Felton February 1, 20126 comments

Last updated 05-Nov-2015

Introduction

From many perspectives the latest FPGA offerings from 'X' and 'A' are large devices - mucho programmable logic resources.  Even the devices that one can get for sub \$10 are relatively large.  Because of the size of these FPGAs they are implemented using an HDL.  To manually configure each circuit would be a long and tedious task.  It is not feasible to program an FPGA by manually defining the logic for each LUT and manually...


VHDL tutorial

Gene Breniman October 4, 20077 comments

When I was first introduced to "Programmable Logic" several years ago, it was an answer to many of the challenges that I was struggling with. Though the parts were primitive by today's standards (simple PALs verses FPGA), they were an extremely cost effective tool addressing the need for specialized logic blocks.

I have continued to incorporate these powerful blocks into many of my latest designs. My current favorite part line is the Xilinx CoolRunner series (XC2Cxxx). In this...


An Editor for HDLs

Dave Vandenbout July 17, 201211 comments

Unless you're still living in the '90s and using schematics, your FPGA designs are entered into text files as VHDL or Verilog source. Which, of course, implies you're using some form of text editor. Now, right after brace placement in C, the choice of an editor is the topic most likely to incite a nerd civil war (it's a bike-shed issue). I won't attempt to influence your choice because it really makes no difference to me. But if you are using the same editor I do, then maybe I can help you...


Developing FPGA-DSP IP with Python

Christopher Felton March 16, 20101 comment

This blog post was previously titled MyHDL ASIC Proven (How is this related to FPGAs?) but the blog post has been updated and mainly discusses developing FPGA-DSP IP with Python / MyHDL. The original content is still present but the post has been reorganized and expanded. Original post 16-Mar-2010.

Developing FPGA-DSP IP with Python / MyHDL

Using Python to develop DSP logic for an FPGA is very powerful. The Python ecosystem contains many packages including numerical and...


MyHDL FPGA Tutorial II (Audio Echo)

Christopher Felton July 18, 2012
Introduction

This tutorial will walk through an audio echo that can be implemented on an FPGA development board.  This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial.  This project will require an FPGA board with an audio codec and the interface logic to the audio codec.

Review the Previous Tutorial

The previous MyHDL FPGA tutorial I posted a strobing LED on an FPGA board.  In that tutorial we introduced the basics of a MyHDL module....


I don’t often convert VHDL to Verilog but when I do ...

Christopher Felton December 24, 20142 comments
VHDL to Verilog

I don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement).  For the most part I am HDL agnostic.  Well that is not true, I have a strong preference for MyHDL, and an insubstantial preference for VHDL over Verilog.  The choice of HDL for a project is often complicated, irrational, sometimes rational, but most often random.  It is often not a choice of the developer - for...


Little to no benefit from C based HLS

Christopher Felton April 5, 2014

Last updated 07-Nov-2015

As I write this I am on a plane and my destination is EELive 2014 where I am going to give a talk hardware design: the grunge era.  It is a shotgun introduction to three alternative hardware description languages (alt.hdl). The three languages briefly introduced in the talk are: bsv, chisel, and myhdl.  The goal of the talk is simply to raise awareness of the three...


Verilog vs VHDL

Muhammad Yasir June 13, 2011

Introduction

 

Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...


Learning VHDL - Basics

Enrico Garante June 15, 20135 comments

Since FPGA are becoming more accessible to the hobbyist, learning how to use them can be really useful for certain applications, like DSP and video generation; moreover, engineers that are able to code in VHDL/Verilog are always requested on the job market.

In this tutorial I will cover the basics of Xilinx ISE and VHDL. I willl base my code on the Basys2 board from Digilent: it is really cheap (especially for students) and has a lot of features on board, as you can see from the picture...


MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)

Christopher Felton September 13, 201210 comments
Introduction

To demonstrate the echo on an FPGA board an interface to an audio ADC/DAC chip will be used. The following will explain the connection to the audio codec and the HDL module used to interface.

Audio Codec Interface

I have two boards with TI AIC23b audio codecs. The AIC23 has a configuration interface (ability to program the registers) and a streaming audio interface. The SPI mode will be used to configure the codec and the I2S interface is used to send and...