MyHDL synthesis: from browser to FPGA in five seconds
Martin Strubel walks through how modern open-source tooling slashes the pain of converting super-HDLs into FPGA-ready firmware. Instead of long translation chains from MyHDL or nMigen into Verilog or VHDL, yosys and its Python API let you build synthesizeable primitives on the fly, inspect schematics, and emit synthesized Verilog or firmware quickly. The post explains the shift from toolchain friction to fast browser-to-FPGA workflows.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
I don’t often convert VHDL to Verilog but when I do ...
Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.
Point of View
Christopher defends a straightforward MyHDL RTL description of a FIR filter, arguing it is explicit, readable, and concise. He compares that style to a functional hardware description built with Python primitives and list comprehensions, and finds both convert to identical synthesis resources for this example. The post highlights readability tradeoffs and suggests choice often comes down to background and preference.
MyHDL Presentation Examples
Christopher Felton collected slide-ready MyHDL demos he used at EELive and PyOhio, making it easy to see practical HDL examples in action. The post explains the tradeoffs behind single-slide examples, links to 2013 and 2014 demos from simple FPGA hello-worlds to filters and a VGA system, and points readers to the repository where full and larger examples live for reuse.
Little to no benefit from C based HLS
Christopher shows why C-based HLS delivers little practical benefit compared with a MyHDL RTL approach, using a Vivado HLS median-filter example. He walks through the sort-network median, compares C and MyHDL implementations, and argues MyHDL is as concise while providing clearer microarchitecture control. The post emphasizes that choosing the right algorithm is the hard part, and HLS won’t replace hardware understanding.
MyHDL Interface Example
Christopher Felton shows how MyHDL 0.9 interfaces bundle Signals into a single bus object to cut connector clutter and simplify module connections. The post walks through a pedagogical example where button presses drive a memory-mapped BareBoneBus read-modify-write that inverts LEDs, with a TDD-style testbench and notes on converting to Verilog/VHDL and loading the example on supported boards.
MyHDL @EDAPlayground
MyHDL just got easier to try: it's available on EDAPlayground, so you can run Python-based HDL verification directly in the browser. The two-panel editor places the testbench on the left and the HDL under test on the right, with public examples such as a simple strobe and a RAM test ready to copy. Christopher Felton also links a curated resource list to help you get started quickly.
Introducing the VPCIe framework
Simulating an embedded CPU and FPGA together is painful when PCI Express is in the middle, so Fabien Le Mentec built VPCIe to virtualize that link. VPCIe traps PCIe accesses from a QEMU-hosted CPU and forwards them to a GHDL-driven VHDL simulation using TCP, letting you run unmodified Linux and drivers against your hardware model. The project is open source on GitHub and supports remote or concurrent device simulations.
Learning VHDL - Basics
Enrico Garante walks through a compact, hands-on introduction to VHDL and Xilinx ISE, using the affordable Basys2 board. The tutorial explains entity versus architecture, the IEEE.STD_LOGIC_1164 types, and how to write a process with a sensitivity list to implement a simple AND gate. A short ISim video demo shows project creation and simulation so you can verify designs before programming the board.
VHDL tutorial
Gene Breniman presents a hands-on VHDL walkthrough for a programmable clock divider implemented on a Xilinx CoolRunner CPLD (XC2C32A). The example shows how to declare ports and internal signals, implement a clock-division process with reset and falling-edge detection, and create a simple addressable latch to select clock rates from a 40MHz master clock. It’s a compact, practical guide for embedded engineers learning VHDL and CPLD design.
MyHDL FPGA Tutorial I (LED Strobe)
Skip Verilog and try MyHDL, a Python-based HDL, to build and simulate an FPGA LED strobe in this hands-on tutorial. Christopher Felton walks through a parameterized LED shifter, py.test driven verification, and automated conversion to Verilog and bitstreams for several development boards. The post includes scripts to generate pin constraints and run vendor tools so you can build and program boards from one language.
I don’t often convert VHDL to Verilog but when I do ...
Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.
Learning VHDL - Basics
Enrico Garante walks through a compact, hands-on introduction to VHDL and Xilinx ISE, using the affordable Basys2 board. The tutorial explains entity versus architecture, the IEEE.STD_LOGIC_1164 types, and how to write a process with a sensitivity list to implement a simple AND gate. A short ISim video demo shows project creation and simulation so you can verify designs before programming the board.
An Editor for HDLs
If you prefer Notepad++ over Emacs, Dave Vandenbout shows how to turn it into a capable HDL editor using templates, a Perl package generator, and Emacs run in batch mode for beautification. He covers FingerText snippets for VHDL skeletons, binding a Perl script to auto-create/update package component declarations, and invoking Emacs from a hotkey to format files with one keystroke.
MyHDL synthesis: from browser to FPGA in five seconds
Martin Strubel walks through how modern open-source tooling slashes the pain of converting super-HDLs into FPGA-ready firmware. Instead of long translation chains from MyHDL or nMigen into Verilog or VHDL, yosys and its Python API let you build synthesizeable primitives on the fly, inspect schematics, and emit synthesized Verilog or firmware quickly. The post explains the shift from toolchain friction to fast browser-to-FPGA workflows.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
Introducing the VPCIe framework
Simulating an embedded CPU and FPGA together is painful when PCI Express is in the middle, so Fabien Le Mentec built VPCIe to virtualize that link. VPCIe traps PCIe accesses from a QEMU-hosted CPU and forwards them to a GHDL-driven VHDL simulation using TCP, letting you run unmodified Linux and drivers against your hardware model. The project is open source on GitHub and supports remote or concurrent device simulations.
MyHDL FPGA Tutorial II (Audio Echo)
Christopher Felton demonstrates how to build an FPGA audio echo using MyHDL by storing delayed samples in BRAM and mixing them back with incoming audio. The project shows parameterizable sample rate, sample width, buffer depth, and conversion from MyHDL to Verilog, with a strong emphasis on test-driven verification and simulation-based resource reports. Read on to see how delay, scaling, and BRAM usage affect real-time audio.
VHDL tutorial
Gene Breniman presents a hands-on VHDL walkthrough for a programmable clock divider implemented on a Xilinx CoolRunner CPLD (XC2C32A). The example shows how to declare ports and internal signals, implement a clock-division process with reset and falling-edge detection, and create a simple addressable latch to select clock rates from a 40MHz master clock. It’s a compact, practical guide for embedded engineers learning VHDL and CPLD design.
MyHDL FPGA Tutorial I (LED Strobe)
Skip Verilog and try MyHDL, a Python-based HDL, to build and simulate an FPGA LED strobe in this hands-on tutorial. Christopher Felton walks through a parameterized LED shifter, py.test driven verification, and automated conversion to Verilog and bitstreams for several development boards. The post includes scripts to generate pin constraints and run vendor tools so you can build and program boards from one language.
I don’t often convert VHDL to Verilog but when I do ...
Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.
An Editor for HDLs
If you prefer Notepad++ over Emacs, Dave Vandenbout shows how to turn it into a capable HDL editor using templates, a Perl package generator, and Emacs run in batch mode for beautification. He covers FingerText snippets for VHDL skeletons, binding a Perl script to auto-create/update package component declarations, and invoking Emacs from a hotkey to format files with one keystroke.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
MyHDL FPGA Tutorial II (Audio Echo)
Christopher Felton demonstrates how to build an FPGA audio echo using MyHDL by storing delayed samples in BRAM and mixing them back with incoming audio. The project shows parameterizable sample rate, sample width, buffer depth, and conversion from MyHDL to Verilog, with a strong emphasis on test-driven verification and simulation-based resource reports. Read on to see how delay, scaling, and BRAM usage affect real-time audio.
Verilog vs VHDL
Muhammad Yasir compares Verilog and VHDL by tracing their history, core features, and global usage to help engineers pick an HDL. The post explains where each language shines: Verilog for concise, low-level IC modeling and faster coding, VHDL for strong typing, packages, and system-level clarity, and it uses Google Trends and market examples to put adoption into context.
Little to no benefit from C based HLS
Christopher shows why C-based HLS delivers little practical benefit compared with a MyHDL RTL approach, using a Vivado HLS median-filter example. He walks through the sort-network median, compares C and MyHDL implementations, and argues MyHDL is as concise while providing clearer microarchitecture control. The post emphasizes that choosing the right algorithm is the hard part, and HLS won’t replace hardware understanding.
Learning VHDL - Basics
Enrico Garante walks through a compact, hands-on introduction to VHDL and Xilinx ISE, using the affordable Basys2 board. The tutorial explains entity versus architecture, the IEEE.STD_LOGIC_1164 types, and how to write a process with a sensitivity list to implement a simple AND gate. A short ISim video demo shows project creation and simulation so you can verify designs before programming the board.
MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
