I work on Zynq 7000 SOC, I know verilog and c languages. I device drivers in C language and verilog. I am into modem development.

Processing Gain at output of ADC

New thread started 9 months ago
With adequate filtering after AD conversion, the SNR is calculated as,SNR=6.02*N+1.76+10*log(fs/(2*BW));N-> No: of ADC bitsThe term 10log(fs/2*BW) is referred...

How to avoid Blocking Statement in Verilog

New thread started 9 months ago
Hi,I have a matlab code and I have to convert it to verilog.The matlab code is as follows:/****************************************************************/clc;clear...

Re: ADC SNR and Processing Gain

Reply posted 9 months ago (05/29/2020)
Hi,Q1)Pass 12 bits data through cic and target 12 bits final output with input/output power unity as a starting point. In the same way treat fir as 12 bits in/out...

ADC SNR and Processing Gain

New thread started 9 months ago
Hi,with reference to the following article,https://www.dsprelated.com/showthread/comp.dsp/727...I have understood that decimating doesn't destroy the processing...

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