Hi, I want to run ModelSim overnight when I am sleeping. How to run an application overnight with the display off in the laptop with Windows...

Hi, I want to run ModelSim overnight when I am sleeping. How to run an application overnight with the display off in the laptop with Windows 10? Is there a shortcut keystroke to turn the screen off while running an application background? Thank you. Weng

Hi, I have a certain interest in a mathematical puzzle that I have not been able to solve using a normal CPU, and I thought that using an...

Hi, I have a certain interest in a mathematical puzzle that I have not been able to solve using a normal CPU, and I thought that using an FPGA could work. For this, I would like to assign some work packages to search for certain numbers to the FPGA, which then processes them and returns the data, plus an indication that it has finished with that particular package. The task at hand i...

Hi, How to turn off the cursor note pane when the cursor stops at the wave pane of ModelSim during simulation? A cursor note pane is shown at...

Hi, How to turn off the cursor note pane when the cursor stops at the wave pane of ModelSim during simulation? A cursor note pane is shown at the wave pane of ModelSim with yellow background color when the cursor stops at a signal line, showing the signal path and name. Thank you. Weng

Hi, Intel ModelSim Starter Edition is available free now! https://fpgasoftware.intel.com/ 10,000 line code limit, VHDL-2002 version,...

Hi, Intel ModelSim Starter Edition is available free now! https://fpgasoftware.intel.com/ 10,000 line code limit, VHDL-2002 version, running speed is very very slow, but it is enough for debugging grammars. It needs to take 3 hours to download Starter Edition part 1 and part 2 of 7.3G, regardless of how your download speed is. Weng

Hi, I have an application where replacing the configuration of the FPGA will occur frequently and hence I do not want to use the built-in...

Hi, I have an application where replacing the configuration of the FPGA will occur frequently and hence I do not want to use the built-in FLASH. Having an always-blank device on the board is perfectly fine. The MachXO2 chip is ideal for many reasons, so I don't want to replace it with a purely SRAM-based FPGA. Now, the "MachXO2 Programming and Configuration Usage Guide" says the FL...

In case you missed it Aldec (Jim Lewis) is doing a webinars series on VHDL2019. https://www.aldec.com/en/company/events It looks like I...

In case you missed it Aldec (Jim Lewis) is doing a webinars series on VHDL2019. https://www.aldec.com/en/company/events It looks like I missed the first one as it start with Part2, Regards, Hans. www.ht-lab.com

Research Assistantship (Fall, 2021) at the Graduate School, Dept. of Comput= er Engineering, Hallym University, Korea The [AI Accelerator...

Research Assistantship (Fall, 2021) at the Graduate School, Dept. of Comput= er Engineering, Hallym University, Korea The [AI Accelerator Design Lab] of the Hallym University seek to recruit pr= omising PhD and MSc or MSc-PhD research students. The selected students will conduct research in the [Hardware Implementation= of Deep Learning Algorithms] and [Deep Learning for Medical Applicat...

What is the correct way to handle a PCIE request to a slow device? I have a xilinx spartan 6 PCIe using Integrated Block for PCI...

What is the correct way to handle a PCIE request to a slow device? I have a xilinx spartan 6 PCIe using Integrated Block for PCI Express. The BAR memory map is decoded and some addresses map to fast ram, or local registers and these work OK, but some addresses map to slow devices.. like I2C or internal processes that need a few cycles to process before they can produce valid data to be ret...

Hi can anyone please tell me how to rectify this error ERROR:MapLib:30 - LOC constraint J17 on topsegF is invalid: No such site on the ...

Hi can anyone please tell me how to rectify this error ERROR:MapLib:30 - LOC constraint J17 on topsegF is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:30 - LOC constraint H14 on topsegG is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:30 - ...

Has anyone used Achronix FPGAs?

Has anyone used Achronix FPGAs?