My code is assigning an incremented unsigned value to an aggregate so the s= um and carry can be extracted without duplicating logic or excessive...

My code is assigning an incremented unsigned value to an aggregate so the s= um and carry can be extracted without duplicating logic or excessive lines = of code (VHDL can be verbose we all know). But it seems this one usage mak= es the Active-HDL simulator complain. I'm adding an integer 1 to the unsig= ned counter value after being resized to be 1 bit larger to match the left = hand side ...

Just had my first taste of the company supplied software from Gowin Semicon= ductor. It's ok. Documentation is terrible being not much more...

Just had my first taste of the company supplied software from Gowin Semicon= ductor. It's ok. Documentation is terrible being not much more than a lis= ting of the menu items. Lots of features are lacking.=20 My test file is a simple 11 bit down counter described three slightly diffe= rent ways to see what might be the best for my current design which is goin= g to have a lot of counters...

One of my guys is suggesting that we ground unused balls on an FPGA and compile them to be low outputs, the idea being to reduce...

One of my guys is suggesting that we ground unused balls on an FPGA and compile them to be low outputs, the idea being to reduce ground impedance and add some damping. Has anyone done this? Does it help? I guess I could have an input that controls the tri-states of all such pins, and also bring out one logic-low to scope, and turn the grounds on and off and see if it makes any difference...

I recently posted a Verilog module to this forum, and someone responded that I was coding at a very low level, which was true; I was referring to...

I recently posted a Verilog module to this forum, and someone responded that I was coding at a very low level, which was true; I was referring to XOR gates, NAND gates, NOR gates, and NOT gates. Is there something wrong with writing my code at such a low level? If I have a fairly good understanding of how my algorithm needs to run at such a low level, then what is wrong with writing

I'm reading reports that AMD is working on buying Xilinx and Qualcom and Broadcom may make bids as well. Stock is up from last week's close of...

I'm reading reports that AMD is working on buying Xilinx and Qualcom and Broadcom may make bids as well. Stock is up from last week's close of $105.99. Other than the company name on documentation I've seen little sign that the Intel purchase of Altera has impacted operations. I wonder if the same can be said for an AMD purchase of Xilinx, or Broadcom or Qualcom. -- Rick C. -...

I'm working on a project with a number of non-EE, non-CE types. A CE mocke= d up a real time simulation of the UI which will be done in the...

I'm working on a project with a number of non-EE, non-CE types. A CE mocke= d up a real time simulation of the UI which will be done in the FPGA. I am= writing the HDL which everyone is nervous about because they know nothing = about FPGAs and have heard too many stories I guess.=20 When the lead heard I was running things in a simulator he asked if it coul= d be interacted with in real ...

I have a time-critical thing where the signal passes through an XC7A15 FPGA and does a fair lot of stuff inside. I measured delay vs...

I have a time-critical thing where the signal passes through an XC7A15 FPGA and does a fair lot of stuff inside. I measured delay vs some voltages: 1.8 aux no measurable DC effect 3.3 vccio no measurable DC effect 2.5 vccio ditto (key io's are LVDS in this bank) +1 core -10 ps per millivolt! If I vary the trigger frequency, I can see the delay heterodyning against the 1....

Try out the PipelineC compiler - it pipelines combinatorial logic for you. https://github.com/JulianKemmerer/PipelineC/wiki It is also a...

Try out the PipelineC compiler - it pipelines combinatorial logic for you. https://github.com/JulianKemmerer/PipelineC/wiki It is also a full hardware description language - thats cool. Looking for folks interested in using or contributing to the project. I need some compiler help :) Super happy to answer questions - thanks folks!

Hi Experts, In FPGA Prototyping/Emulation flows, Multi-FPGA partitioning puts limitation on performance due to limited IO pins. What are the...

Hi Experts, In FPGA Prototyping/Emulation flows, Multi-FPGA partitioning puts limitation on performance due to limited IO pins. What are the latest Multi-FPGA Interconnection techniques available today? By using Multi Gigabit Transceivers , how much performance improvement is expected ? Thanks in Advance Parth

I have a design in mind that would fit in this skeleton: [code] module xyz ( result, leftOp, rightOp); parameter integer nmBits =...

I have a design in mind that would fit in this skeleton: [code] module xyz ( result, leftOp, rightOp); parameter integer nmBits = 1; localparam integer highBit = nmBits - 1; output result; input [ highBit:0] leftOp; input [ highBit:0] rightOp; // ... endmodule [/code] The way (xyz) is designed, this module would work differently for different values of (nmBits),