Advice to a newbie

On 5/27/2016 10:46 PM, jim.brakefield@ieee.org wrote:
> On Friday, May 27, 2016 at 8:27:34 PM UTC-5, Cecil Bayona wrote:

>> The disadvantage to all these simple CPUs is that there is no
>> documentation to the software that creates the devices so as a rank
>> beginner it will be difficult to see what they are doing.
>>
>> Thanks
>> --
>> Cecil - k5nwa
>
> ]>The disadvantage to all these simple CPUs is that there is no
> ]> documentation to the software that creates the devices so as a rank
> ]> beginner it will be difficult to see what they are doing.
>
> Did a presentation in March directed towards this problem.  The idea is to do
>  the simplest possible soft core processor (done here in VHDL).  It helps to
>  use the fewest lines of code.  The PDF of the slides is at:
>  http://opencores.org/project,rois,downloads  "DIY soft-core processor"
> Full VHDL code is available on the Overview section.  Only four instructions
>  are implemented (didn't want to make it too easy for students).
>
> If you enjoy doing test cases and would like to help, send an e-mail.
>
> Jim Brakefield
>
Thanks for the link, I will look at it this weekend, every little bit helps.

  I watched a series of YouTube videos and there is hope, a small 
project but not idiot simple and done by hand, it didn't seen as alien 
as I thought it would be. The person basically designed the hardware and 
then proceeded to generate the program with explanation of what he was 
doing, of course the devil hides in the details but still it looked 
logical and not difficult. So after the weekend I will try it out. This 
weekend I will be following a seminar on the ep8080 CPU, a high 
performance clone of the 8080 CPU not only does it run at higher speed 
but most instructions execute in one clock cycle, it should be interesting.

-- 
Cecil - k5nwa

On 5/27/2016 9:30 PM, Cecil Bayona wrote:
> On 5/27/2016 8:27 PM, Cecil Bayona wrote:
>>>
>> It looks like I didn't make myself clear enough on what I was looking
>> for, I was looking for books or articles on FPGA programming that
>> discusses how to use the software to program the FPGA to create CPU
>> features. I already own a few books and have many articles on CPU
>> architecture, plus books and literature on CPU instruction sets.
>>
>> Is there literature,basically a primer on how to create a simple CPU in
>> HDL, preferably in VHDL?
>>
>> The alternative is that I will need to do it on my own by looking at a
>> simple example such as the J1 , ep16,  or the B16 CPUs and see what they
>> are doing to create the CPU hardware blocks. The J1 is a pretty simple
>> CPU done in less than 250 Verilog statements, the instructions are are
>> bits controlling the various hardware features with no decoding of the
>> instructions.The J16 is done in VHDL using a Lattice Brevia2 so it
>> should run as is, the disadvantage is that it's more complex plus it's
>> created by someone who is not very experienced. All three already have a
>> compiler available to write software to test them.
>
> Sorry it the ep16 instead of the J16 that is in VHDL and uses a Lattice
> Brevia2 board.
>
>>
>> The disadvantage to all these simple CPUs is that there is no
>> documentation to the software that creates the devices so as a rank
>> beginner it will be difficult to see what they are doing.

I have not seen any books on this topic, but then I haven't looked.  My 
approach is not study the architectures of various approaches to soft 
CPUs and adapt to suit my needs.  I did some work on a MISC (minimal 
instruction set computer) around 2001, 2002.  I found that there were 
others doing the same thing and we were all discovering the same issues. 
  Our approaches differed mainly in what our priorities were.

I ended up dropping further work to a large extent.  I did play with 
some ideas a few years ago regarding an architecture that included 
fields in the instruction for small offsets from the stack pointer to 
try to combine the advantages of register and stack machines.  I think 
it has potential for working well at the hardware level.  I just don't 
know enough about compiler writing to program this device from a 
compiler.  Maybe I'll get back to this again some day.

In the meantime, I suggest you work with existing CPU designs to learn 
what they have done.  No point in reinventing the wheel.  The group 
comp.lang.forth has a few folks who have designed their own CPUs which 
you seem to already be aware of.  However, this is a good group to 
discuss your issues.

I would not worry about the target device.  The HDL isolates you nicely 
from the hardware unless you wish to highly optimize the design for a 
particular FPGA family.  The fact that some design was implemented on a 
Brevia2 board really doesn't matter and can also be run on a Spartan, 
Cyclone or Fusion.

-- 

Rick C

On Sat, 28 May 2016 10:06:47 -0400, rickman wrote:

> On 5/27/2016 9:30 PM, Cecil Bayona wrote:
>> On 5/27/2016 8:27 PM, Cecil Bayona wrote:
>>>>
>>> It looks like I didn't make myself clear enough on what I was looking
>>> for, I was looking for books or articles on FPGA programming that
>>> discusses how to use the software to program the FPGA to create CPU
>>> features. I already own a few books and have many articles on CPU
>>> architecture, plus books and literature on CPU instruction sets.
>>>
>>> Is there literature,basically a primer on how to create a simple CPU
>>> in HDL, preferably in VHDL?
>>>
>>> The alternative is that I will need to do it on my own by looking at a
>>> simple example such as the J1 , ep16,  or the B16 CPUs and see what
>>> they are doing to create the CPU hardware blocks. The J1 is a pretty
>>> simple CPU done in less than 250 Verilog statements, the instructions
>>> are are bits controlling the various hardware features with no
>>> decoding of the instructions.The J16 is done in VHDL using a Lattice
>>> Brevia2 so it should run as is, the disadvantage is that it's more
>>> complex plus it's created by someone who is not very experienced. All
>>> three already have a compiler available to write software to test
>>> them.
>>
>> Sorry it the ep16 instead of the J16 that is in VHDL and uses a Lattice
>> Brevia2 board.
>>
>>
>>> The disadvantage to all these simple CPUs is that there is no
>>> documentation to the software that creates the devices so as a rank
>>> beginner it will be difficult to see what they are doing.
> 
> I have not seen any books on this topic, but then I haven't looked.  My
> approach is not study the architectures of various approaches to soft
> CPUs and adapt to suit my needs.  I did some work on a MISC (minimal
> instruction set computer) around 2001, 2002.  I found that there were
> others doing the same thing and we were all discovering the same issues.
>   Our approaches differed mainly in what our priorities were.
> 
> I ended up dropping further work to a large extent.  I did play with
> some ideas a few years ago regarding an architecture that included
> fields in the instruction for small offsets from the stack pointer to
> try to combine the advantages of register and stack machines.  I think
> it has potential for working well at the hardware level.  I just don't
> know enough about compiler writing to program this device from a
> compiler.  Maybe I'll get back to this again some day.

Ages ago I had a notion about combining the advantages of register and 
stack machines, which was to call the region of 16 addresses around the 
stack "registers", and to have the processor automagically cache them on 
a context switch.  The idea was that the code itself wouldn't have to 
specify registers to save on push and pop because the processor would do 
it automatically.

I'm pretty sure I had not yet seen, nor independently conceive, the RISC-
ish push & pop of multiple registers in one instruction.

-- 
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work!  See my website if you're interested
http://www.wescottdesign.com

On 5/28/2016 9:06 AM, rickman wrote:
> On 5/27/2016 9:30 PM, Cecil Bayona wrote:

>>>
>>> The disadvantage to all these simple CPUs is that there is no
>>> documentation to the software that creates the devices so as a rank
>>> beginner it will be difficult to see what they are doing.
>
> I have not seen any books on this topic, but then I haven't looked.  My
> approach is not study the architectures of various approaches to soft
> CPUs and adapt to suit my needs.  I did some work on a MISC (minimal
> instruction set computer) around 2001, 2002.  I found that there were
> others doing the same thing and we were all discovering the same issues.
>  Our approaches differed mainly in what our priorities were.

I've found a couple of YouTube videos to help me get started, I'm 
looking at Amazon for books on the basics of VHDL so I'm sure that I 
will find enough to get started, the videos made it look easy if you are 
familiar with hardware design.
>
> I ended up dropping further work to a large extent.  I did play with
> some ideas a few years ago regarding an architecture that included
> fields in the instruction for small offsets from the stack pointer to
> try to combine the advantages of register and stack machines.  I think
> it has potential for working well at the hardware level.  I just don't
> know enough about compiler writing to program this device from a
> compiler.  Maybe I'll get back to this again some day.
>
> In the meantime, I suggest you work with existing CPU designs to learn
> what they have done.  No point in reinventing the wheel.  The group
> comp.lang.forth has a few folks who have designed their own CPUs which
> you seem to already be aware of.  However, this is a good group to
> discuss your issues.

That is my plan, I mentioned several simple CPUs before that are very 
small, and have software available to be able to test them without 
re-inventing the wheel.  I would get them going, try to understand then, 
then start making modifications, then create one from scratch, simple at 
first then add improvements, it will take a while but that is part of 
the learning process.
>
> I would not worry about the target device.  The HDL isolates you nicely
> from the hardware unless you wish to highly optimize the design for a
> particular FPGA family.  The fact that some design was implemented on a
> Brevia2 board really doesn't matter and can also be run on a Spartan,
> Cyclone or Fusion.
>

For most of what I'm interested in you are right, mostly simple 
architectures that are lean and mean with nothing fancy, memory, 
registers, ALU units, and multiplexers, everybody has those devices, 
some boards have lot's of IO devices such as VGA, external RAM, etc but 
for now all I need is some RAM, and a serial port which the Brevia2 
already has.

An exiting adventure, I should have started on this earlier but today is 
better than tomorrow.
-- 
Cecil - k5nwa

On 5/28/2016 1:08 PM, Cecil Bayona wrote:
> On 5/28/2016 9:06 AM, rickman wrote:
>> On 5/27/2016 9:30 PM, Cecil Bayona wrote:
>
>>>>
>>>> The disadvantage to all these simple CPUs is that there is no
>>>> documentation to the software that creates the devices so as a rank
>>>> beginner it will be difficult to see what they are doing.
>>
>> I have not seen any books on this topic, but then I haven't looked.  My
>> approach is not study the architectures of various approaches to soft
>> CPUs and adapt to suit my needs.  I did some work on a MISC (minimal
>> instruction set computer) around 2001, 2002.  I found that there were
>> others doing the same thing and we were all discovering the same issues.
>>  Our approaches differed mainly in what our priorities were.
>
> I've found a couple of YouTube videos to help me get started, I'm
> looking at Amazon for books on the basics of VHDL so I'm sure that I
> will find enough to get started, the videos made it look easy if you are
> familiar with hardware design.

I think the need for a book is a bit overrated these days.  I haven't 
opened a VHDL book in ages.  When I don't recall something or I want to 
learn about new features (VHDL 2008 has many) I just do a google search.

You can also get plenty of help here and in c.l.vhdl.


>> I ended up dropping further work to a large extent.  I did play with
>> some ideas a few years ago regarding an architecture that included
>> fields in the instruction for small offsets from the stack pointer to
>> try to combine the advantages of register and stack machines.  I think
>> it has potential for working well at the hardware level.  I just don't
>> know enough about compiler writing to program this device from a
>> compiler.  Maybe I'll get back to this again some day.
>>
>> In the meantime, I suggest you work with existing CPU designs to learn
>> what they have done.  No point in reinventing the wheel.  The group
>> comp.lang.forth has a few folks who have designed their own CPUs which
>> you seem to already be aware of.  However, this is a good group to
>> discuss your issues.
>
> That is my plan, I mentioned several simple CPUs before that are very
> small, and have software available to be able to test them without
> re-inventing the wheel.  I would get them going, try to understand then,
> then start making modifications, then create one from scratch, simple at
> first then add improvements, it will take a while but that is part of
> the learning process.

What is your end goal?  The main reason I quit working on my own was 
that I was not finding much room for improvement other than application 
specific features or optimizations.  The target space has been explored 
pretty well at this point.

The J1 is a great little processor.  Then there is the ZPU which doesn't 
come up much in Forth circles, but is a stack machine programmed in C.


>> I would not worry about the target device.  The HDL isolates you nicely
>> from the hardware unless you wish to highly optimize the design for a
>> particular FPGA family.  The fact that some design was implemented on a
>> Brevia2 board really doesn't matter and can also be run on a Spartan,
>> Cyclone or Fusion.
>>
>
> For most of what I'm interested in you are right, mostly simple
> architectures that are lean and mean with nothing fancy, memory,
> registers, ALU units, and multiplexers, everybody has those devices,
> some boards have lot's of IO devices such as VGA, external RAM, etc but
> for now all I need is some RAM, and a serial port which the Brevia2
> already has.
>
> An exiting adventure, I should have started on this earlier but today is
> better than tomorrow.

The workshop should have started by now.  I haven't see an email from 
SVFIG yet.

-- 

Rick C

On 5/28/2016 1:22 PM, rickman wrote:
> On 5/28/2016 1:08 PM, Cecil Bayona wrote:
>> On 5/28/2016 9:06 AM, rickman wrote:
>>> On 5/27/2016 9:30 PM, Cecil Bayona wrote:
>>
>>>>>
>>>>> The disadvantage to all these simple CPUs is that there is no
>>>>> documentation to the software that creates the devices so as a rank
>>>>> beginner it will be difficult to see what they are doing.
>>>
>>> I have not seen any books on this topic, but then I haven't looked.  My
>>> approach is not study the architectures of various approaches to soft
>>> CPUs and adapt to suit my needs.  I did some work on a MISC (minimal
>>> instruction set computer) around 2001, 2002.  I found that there were
>>> others doing the same thing and we were all discovering the same issues.
>>>  Our approaches differed mainly in what our priorities were.
>>
>> I've found a couple of YouTube videos to help me get started, I'm
>> looking at Amazon for books on the basics of VHDL so I'm sure that I
>> will find enough to get started, the videos made it look easy if you are
>> familiar with hardware design.
>
> I think the need for a book is a bit overrated these days.  I haven't
> opened a VHDL book in ages.  When I don't recall something or I want to
> learn about new features (VHDL 2008 has many) I just do a google search.
>
> You can also get plenty of help here and in c.l.vhdl.
>
>
>>> I ended up dropping further work to a large extent.  I did play with
>>> some ideas a few years ago regarding an architecture that included
>>> fields in the instruction for small offsets from the stack pointer to
>>> try to combine the advantages of register and stack machines.  I think
>>> it has potential for working well at the hardware level.  I just don't
>>> know enough about compiler writing to program this device from a
>>> compiler.  Maybe I'll get back to this again some day.
>>>
>>> In the meantime, I suggest you work with existing CPU designs to learn
>>> what they have done.  No point in reinventing the wheel.  The group
>>> comp.lang.forth has a few folks who have designed their own CPUs which
>>> you seem to already be aware of.  However, this is a good group to
>>> discuss your issues.
>>
>> That is my plan, I mentioned several simple CPUs before that are very
>> small, and have software available to be able to test them without
>> re-inventing the wheel.  I would get them going, try to understand then,
>> then start making modifications, then create one from scratch, simple at
>> first then add improvements, it will take a while but that is part of
>> the learning process.
>
> What is your end goal?  The main reason I quit working on my own was
> that I was not finding much room for improvement other than application
> specific features or optimizations.  The target space has been explored
> pretty well at this point.
>
> The J1 is a great little processor.  Then there is the ZPU which doesn't
> come up much in Forth circles, but is a stack machine programmed in C.
>
>
>>> I would not worry about the target device.  The HDL isolates you nicely
>>> from the hardware unless you wish to highly optimize the design for a
>>> particular FPGA family.  The fact that some design was implemented on a
>>> Brevia2 board really doesn't matter and can also be run on a Spartan,
>>> Cyclone or Fusion.
>>>
>>
>> For most of what I'm interested in you are right, mostly simple
>> architectures that are lean and mean with nothing fancy, memory,
>> registers, ALU units, and multiplexers, everybody has those devices,
>> some boards have lot's of IO devices such as VGA, external RAM, etc but
>> for now all I need is some RAM, and a serial port which the Brevia2
>> already has.
>>
>> An exiting adventure, I should have started on this earlier but today is
>> better than tomorrow.
>
> The workshop should have started by now.  I haven't see an email from
> SVFIG yet.

Found it. I had to search youtube for "svfig may"

https://www.youtube.com/watch?v=rhgCrnF036Y


-- 

Rick C

On 5/28/2016 12:22 PM, rickman wrote:
> On 5/28/2016 1:08 PM, Cecil Bayona wrote:

>> I've found a couple of YouTube videos to help me get started, I'm
>> looking at Amazon for books on the basics of VHDL so I'm sure that I
>> will find enough to get started, the videos made it look easy if you are
>> familiar with hardware design.
>
> I think the need for a book is a bit overrated these days.  I haven't
> opened a VHDL book in ages.  When I don't recall something or I want to
> learn about new features (VHDL 2008 has many) I just do a google search.
>
> You can also get plenty of help here and in c.l.vhdl.
>
>

I bought a couple of used VHDL books on Amazon for good prices. I agree 
once you get going the need for the book diminishes that is why I bought 
used books, the Internet is a good source of information once you know 
the basics.

>> That is my plan, I mentioned several simple CPUs before that are very
>> small, and have software available to be able to test them without
>> re-inventing the wheel.  I would get them going, try to understand then,
>> then start making modifications, then create one from scratch, simple at
>> first then add improvements, it will take a while but that is part of
>> the learning process.
>
> What is your end goal?  The main reason I quit working on my own was
> that I was not finding much room for improvement other than application
> specific features or optimizations.  The target space has been explored
> pretty well at this point.
>
> The J1 is a great little processor.  Then there is the ZPU which doesn't
> come up much in Forth circles, but is a stack machine programmed in C.
>
>
My end goal is simple, I do it for my pleasure, no vital need here other 
than keeping your mind active and busy. I enjoy creating things so this 
will go a long way to satisfy that desire without a whole lot of expenses.

I will look into the ZPU, I saw some references to it but I will look 
into it, I have two choices to start with, the J1, and the ep16


-- 
Cecil - k5nwa

On Friday, May 27, 2016 at 11:10:26 PM UTC-4, rickman wrote:
> This does not directly address your stated issues, but there is a 
> workshop Saturday.  Notable is that it will use the same starter kit you 
> have.  I believe you can participate via the Internet.  It might be 
> interesting to you since it is about CPU design.  Here is a post I made 
> about this in another group.
> 
> Dr. Ting will be leading a workshop on using a Lattice FPGA to implement 
> an emulation of the 8080 instruction set which will run Forth.
> 
> http://www.meetup.com/SV-FIG/events/229926249/
> 
> I believe you need to be a member of Meetup to see this page.  I'm not 
> sure but you may need to be a member of the SVFIG meetup group as well. 
> There is no charge to join either.

Thank you for posting this information, Rick C.  I've watched some of
the content that's available on YouTube from the event.  It's very
interesting.

Best regards,
Rick C. Hodgin

On 5/28/2016 6:37 PM, Rick C. Hodgin wrote:
> On Friday, May 27, 2016 at 11:10:26 PM UTC-4, rickman wrote:
>> This does not directly address your stated issues, but there is a
>> workshop Saturday.  Notable is that it will use the same starter kit you
>> have.  I believe you can participate via the Internet.  It might be
>> interesting to you since it is about CPU design.  Here is a post I made
>> about this in another group.
>>
>> Dr. Ting will be leading a workshop on using a Lattice FPGA to implement
>> an emulation of the 8080 instruction set which will run Forth.
>>
>> http://www.meetup.com/SV-FIG/events/229926249/
>>
>> I believe you need to be a member of Meetup to see this page.  I'm not
>> sure but you may need to be a member of the SVFIG meetup group as well.
>> There is no charge to join either.
>
> Thank you for posting this information, Rick C.  I've watched some of
> the content that's available on YouTube from the event.  It's very
> interesting.
>
> Best regards,
> Rick C. Hodgin
>
Thanks for the info, but I was aware of the workshop and bought the 
Brevia2 so I could participate in the workshop, I missed part of the 
afternoon session as an emergency cropped up but I was planning on later 
in the week watch the video and follow along. with the video I can stop, 
wind back and take my time in following along. Previous to the workshop 
I loaded the software and got it working, so my goal is to go over the 
explanations on what the different sections do.

-- 
Cecil - k5nwa

On 5/28/2016 12:22 PM, rickman wrote:

>> I've found a couple of YouTube videos to help me get started, I'm
>> looking at Amazon for books on the basics of VHDL so I'm sure that I
>> will find enough to get started, the videos made it look easy if you are
>> familiar with hardware design.
>
> I think the need for a book is a bit overrated these days.  I haven't
> opened a VHDL book in ages.  When I don't recall something or I want to
> learn about new features (VHDL 2008 has many) I just do a google search.
>
> You can also get plenty of help here and in c.l.vhdl.
>
>
I have several book on the way that are used and cost little so between 
them I should have plenty of information. I also got two used books on 
computer architecture that look interesting for next to nothing, overall 
I paid $54 for 7 hard bound books, some are new, or close to new in 
condition. I also went through my bookshelf and I found two books that 
look decent, one looks pretty nice it goes through the feature of VHDL 
on their use, "VHDL Made Easy". The second one is "HDL Chip Design" and 
it looks very useful, it goes discussing various hardware features and 
covers how to implement them in VHDL, and Verilog. Both books are brand 
new that I purchase on Amazon for less than $10

So it looks like I will have a decent reference library for not much. 
This coming week will be time to experiment. I've setup a Virtual 
Windows 7machine with VMware on two I7 PC's and they seem to be working 
fine.


-- 
Cecil - k5nwa