> > UDP/IP is much simpler the TCP/IP. It is commonly done in FPGAs. > > For example: > > http://www.fpga4fun.com/10BASE-T.html > > OK. It is only 10Base-T. But it's not that different than the 10GbE that > we do. > > You can get a crappy NIC and Basys 3 Artix 7 board for less than $200.00 > > http://store.digilentinc.com/pmodnic100-network-interface-controller/ > > It won't be low latency (the NIC has an SPI serial interface) but it > will teach concepts. > > Rob.Thanks. Is this the board you are referring to? http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/ If so, this board doesn't seem to have SPI (at least no listed in the description). Also, do you think this board has enough capacity (in terms of logic elements, etc.) to support a fairly complicated design like UDP/IP?
Help me choose an FPGA to design network protocols
Started by ●August 26, 2016
Reply by ●August 29, 20162016-08-29
Reply by ●August 29, 20162016-08-29
PM X <pinaki2@gmail.com> wrote:> As a matter of fact, I am doing this to prepare myself for interviews in > FPGA design role in high frequency trading (in maybe 3-6 months time). Is > there any simpler project that you could suggest that would be in the > general area of network protocols (maybe like a stripped down version) > that could be implemented in FPGA? Thanks!I'd start bottom-up. First, get the PHY working. You probably want a single speed without any rate switching (eg 1G, 10G), because anything else gets messy with clock reconfiguration. The choice will likely depend on your board. (You can't really test it at this point). Hopefully your board vendor has example code for this. Then drop in a vendor MAC component. I've used the Altera ones and they're not too bad: there are pipes on the side for streams in and out which are easy to deal with. There is a memory mapped interface for configuration - you may need to implement that to configure it, or maybe the defaults are OK. (To configure, use a soft core - NIOS or Microblaze or whatever). On the subject of board choice, I'd suggest avoiding anything with an external MAC chip (external PHY is OK) because they expect to be driven from a processor, while on FPGA it's all about packet pipes. Likewise a MAC as part of a CPU subsystem (eg a Zynq PS, Altera SoC-FPGA HPS) should be avoided because they usually have the same problem, as well as being awkward poorly-documented third-party IP where you essentially have to use the Linux driver. Once you have the MAC working, you have layer 2 packets in and out (you can see MAC addresses etc). Then you can start building up the layers (eg do IP and ARP). The MAC will probably give you some help for layer 2 (eg compute checksums for you) but you're on your own after that. Building up the layers is something you can simulate, while doing the plumbing of the MAC you can only test in hardware. I'd suggest writing a testbench that simulates pushing layer 2 packets between two simulated endpoints, and you can replace that by MAC+PHY on hardware when necessary. If you want experience of networking on FPGA, you don't need to do a full TCP stack to do that: much of the principles of pushing packets about and dealing with vendor IP cores is the same irrespective of the packet format. If it makes you think about latency and meeting timing, that's a useful thing. If you want to learn about the vagaries of TCP, IPv6, etc I'd suggest starting from software first. Maybe find some NIC with a non-scary interface and program it directly (with no OS support). I'm thinking something old like a PCI NE2000 (eg RTL8139) that isn't as complex as a modern card - the Intel gigabit E1000(e) series (8254x, 8257x, I21x) are well documented but a bit more complex. While you can do this from FPGA, it's much harder to debug. Theo
Reply by ●August 29, 20162016-08-29
On 8/26/2016 5:47 PM, PM X wrote:> Hi all, > I have over a decade of experience in hardware design, but almost all of it is in ASIC. I had done some FPGA projects in school, but nothing after that. So after all these years, I want to work on some personal FPGA projects (mainly to prepare myself for future job interviews). I have the following two questions. > > 1. What is an FPGA board that I can buy for this purpose? I am probably looking to do something not too basic (since I already have a lot of experience in design), at the same time I do not want to make it a super complicated full time project either. I prefer Xilinx (but I am open) and something less than $250 will be good. Note that question #2 might also affect the choice of board. > > 2. Once I have the FPGA board, I would like to implement some design involving network protocol (like TCP/IP, UDP, etc.). However, I have not worked on these network layers before and don't have an extensive knowledge on them either (other than what I had read in school long ago), so I do not have a very clear picture of what to do. Is there any open source design available on this? Or any projects with specific definitions that I can understand and then start implementing? > > Thanks! >Right off the bat I'm not much of an expert so maybe some that are more experienced can comment. Have you looked at the Digilent Arty Artix 7 FPGA board? It's inexpensive at $99, and has a built in Ethernet Physical, and it mentions that it comes with A MAC IP so you are off to a start. It has 35K cells so I'm not familiar if that would be enough to implement the rest of the needed logic. It has both Arduino, and Pmod connectors so if desired you can add an external Ethernet module that are available in several chip versions. < http://store.digilentinc.com/arty-board-artix-7-fpga-development-board-for-makers-and-hobbyists/ > Here is one external Ethernet adapter, there are many other available from other places. < http://store.digilentinc.com/pmodnic100-network-interface-controller/ > -- Cecil - k5nwa
Reply by ●August 29, 20162016-08-29
On 8/29/2016 4:58 AM, PM X wrote:>> >> UDP/IP is much simpler the TCP/IP. It is commonly done in FPGAs. >> >> For example: >> >> http://www.fpga4fun.com/10BASE-T.html >> >> OK. It is only 10Base-T. But it's not that different than the 10GbE that >> we do. >> >> You can get a crappy NIC and Basys 3 Artix 7 board for less than $200.00 >> >> http://store.digilentinc.com/pmodnic100-network-interface-controller/ >> >> It won't be low latency (the NIC has an SPI serial interface) but it >> will teach concepts. >> >> Rob. > > Thanks. Is this the board you are referring to? > http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/ > > If so, this board doesn't seem to have SPI (at least no listed in the description). Also, do you think this board has enough capacity (in terms of logic elements, etc.) to support a fairly complicated design like UDP/IP?What do you mean it doesn't have SPI? SPI is a simple shift register interface which can *easily* be implemented in an FPGA (or MCU) using the GPIOs. Do you mean ISP, in system programming? If it doesn't have ISP how do you load your design? -- Rick C
Reply by ●August 29, 20162016-08-29
On 8/29/2016 1:32 PM, rickman wrote:> On 8/29/2016 4:58 AM, PM X wrote: >>> >>> UDP/IP is much simpler the TCP/IP. It is commonly done in FPGAs. >>> >>> For example: >>> >>> http://www.fpga4fun.com/10BASE-T.html >>> >>> OK. It is only 10Base-T. But it's not that different than the 10GbE that >>> we do. >>> >>> You can get a crappy NIC and Basys 3 Artix 7 board for less than $200.00 >>> >>> http://store.digilentinc.com/pmodnic100-network-interface-controller/ >>> >>> It won't be low latency (the NIC has an SPI serial interface) but it >>> will teach concepts. >>> >>> Rob. >> >> Thanks. Is this the board you are referring to? >> http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/ >> >> >> If so, this board doesn't seem to have SPI (at least no listed in the >> description). Also, do you think this board has enough capacity (in >> terms of logic elements, etc.) to support a fairly complicated design >> like UDP/IP? > > What do you mean it doesn't have SPI? SPI is a simple shift register > interface which can *easily* be implemented in an FPGA (or MCU) using > the GPIOs. > > Do you mean ISP, in system programming? If it doesn't have ISP how do > you load your design? >It's a FPGA, you can add SPI easily, there are IPs for free to allow that to happen. In my post I was also going to mention the BASYS-3 board, I left it out because the Arty Board has a ton of memory available that this one doesn't but this on has a lot of switches and LED which can be handy. -- Cecil - k5nwa
Reply by ●August 29, 20162016-08-29
On Monday, August 29, 2016 at 11:32:23 AM UTC-7, rickman wrote:> On 8/29/2016 4:58 AM, PM X wrote: > >> > >> UDP/IP is much simpler the TCP/IP. It is commonly done in FPGAs. > >> > >> For example: > >> > >> http://www.fpga4fun.com/10BASE-T.html > >> > >> OK. It is only 10Base-T. But it's not that different than the 10GbE that > >> we do. > >> > >> You can get a crappy NIC and Basys 3 Artix 7 board for less than $200.00 > >> > >> http://store.digilentinc.com/pmodnic100-network-interface-controller/ > >> > >> It won't be low latency (the NIC has an SPI serial interface) but it > >> will teach concepts. > >> > >> Rob. > > > > Thanks. Is this the board you are referring to? > > http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/ > > > > If so, this board doesn't seem to have SPI (at least no listed in the description). Also, do you think this board has enough capacity (in terms of logic elements, etc.) to support a fairly complicated design like UDP/IP? > > What do you mean it doesn't have SPI? SPI is a simple shift register > interface which can *easily* be implemented in an FPGA (or MCU) using > the GPIOs. > > Do you mean ISP, in system programming? If it doesn't have ISP how do > you load your design? > > -- > > Rick CI meant I didn't see a (dedicated) SPI interface. But you're right. SPI protocol just needs 4 general purpose pins, so using GPIOs should do it.
Reply by ●August 29, 20162016-08-29
On Monday, August 29, 2016 at 11:38:27 AM UTC-7, Cecil Bayona wrote:> On 8/29/2016 1:32 PM, rickman wrote: > > On 8/29/2016 4:58 AM, PM X wrote: > >>> > >>> UDP/IP is much simpler the TCP/IP. It is commonly done in FPGAs. > >>> > >>> For example: > >>> > >>> http://www.fpga4fun.com/10BASE-T.html > >>> > >>> OK. It is only 10Base-T. But it's not that different than the 10GbE that > >>> we do. > >>> > >>> You can get a crappy NIC and Basys 3 Artix 7 board for less than $200.00 > >>> > >>> http://store.digilentinc.com/pmodnic100-network-interface-controller/ > >>> > >>> It won't be low latency (the NIC has an SPI serial interface) but it > >>> will teach concepts. > >>> > >>> Rob. > >> > >> Thanks. Is this the board you are referring to? > >> http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/ > >> > >> > >> If so, this board doesn't seem to have SPI (at least no listed in the > >> description). Also, do you think this board has enough capacity (in > >> terms of logic elements, etc.) to support a fairly complicated design > >> like UDP/IP? > > > > What do you mean it doesn't have SPI? SPI is a simple shift register > > interface which can *easily* be implemented in an FPGA (or MCU) using > > the GPIOs. > > > > Do you mean ISP, in system programming? If it doesn't have ISP how do > > you load your design? > > > > It's a FPGA, you can add SPI easily, there are IPs for free to allow > that to happen. > > In my post I was also going to mention the BASYS-3 board, I left it out > because the Arty Board has a ton of memory available that this one > doesn't but this on has a lot of switches and LED which can be handy. > -- > Cecil - k5nwaOK, thanks. I will check out both of them. What is the largest design you (or someone you know) have implemented on these boards? The Artix line seems to be lower end than Virtex line, so trying to get an idea if they can support somewhat complicated designs.
Reply by ●August 29, 20162016-08-29
On 8/29/2016 2:40 PM, PM X wrote:> On Monday, August 29, 2016 at 11:38:27 AM UTC-7, Cecil Bayona wrote: >> On 8/29/2016 1:32 PM, rickman wrote: >>> On 8/29/2016 4:58 AM, PM X wrote: >>>>> >>>>> UDP/IP is much simpler the TCP/IP. It is commonly done in FPGAs. >>>>> >>>>> For example: >>>>> >>>>> http://www.fpga4fun.com/10BASE-T.html >>>>> >>>>> OK. It is only 10Base-T. But it's not that different than the 10GbE that >>>>> we do. >>>>> >>>>> You can get a crappy NIC and Basys 3 Artix 7 board for less than $200.00 >>>>> >>>>> http://store.digilentinc.com/pmodnic100-network-interface-controller/ >>>>> >>>>> It won't be low latency (the NIC has an SPI serial interface) but it >>>>> will teach concepts. >>>>> >>>>> Rob. >>>> >>>> Thanks. Is this the board you are referring to? >>>> http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/ >>>> >>>> >>>> If so, this board doesn't seem to have SPI (at least no listed in the >>>> description). Also, do you think this board has enough capacity (in >>>> terms of logic elements, etc.) to support a fairly complicated design >>>> like UDP/IP? >>> >>> What do you mean it doesn't have SPI? SPI is a simple shift register >>> interface which can *easily* be implemented in an FPGA (or MCU) using >>> the GPIOs. >>> >>> Do you mean ISP, in system programming? If it doesn't have ISP how do >>> you load your design? >>> >> >> It's a FPGA, you can add SPI easily, there are IPs for free to allow >> that to happen. >> >> In my post I was also going to mention the BASYS-3 board, I left it out >> because the Arty Board has a ton of memory available that this one >> doesn't but this on has a lot of switches and LED which can be handy. >> -- >> Cecil - k5nwa > > OK, thanks. I will check out both of them. What is the largest design you (or someone you know) have implemented on these boards? The Artix line seems to be lower end than Virtex line, so trying to get an idea if they can support somewhat complicated designs. >Nothing Fancy, that is why in my earlier post I mentioned that I don't have a lot of experience. I been working a 32 bit stack based CPU, but it's a work in progress, I'm still sorting it out, it taken less than 20% of the chip, but a stack CPU are rather simple compared to other CPU's, when finished it should be pretty nice, most instructions take one clock to execute, and it used packed instructions, 5 instructions to a word fetch. Originally it was on a Lattice Brevia2, I am now converting it to a Artix-7 board, but there is software involved too so it's going slow and I'm learning as I go. -- Cecil - k5nwa
Reply by ●August 29, 20162016-08-29
On 8/29/2016 3:40 PM, PM X wrote:> On Monday, August 29, 2016 at 11:38:27 AM UTC-7, Cecil Bayona wrote: >> On 8/29/2016 1:32 PM, rickman wrote: >>> On 8/29/2016 4:58 AM, PM X wrote: >>>>> >>>>> UDP/IP is much simpler the TCP/IP. It is commonly done in FPGAs. >>>>> >>>>> For example: >>>>> >>>>> http://www.fpga4fun.com/10BASE-T.html >>>>> >>>>> OK. It is only 10Base-T. But it's not that different than the 10GbE that >>>>> we do. >>>>> >>>>> You can get a crappy NIC and Basys 3 Artix 7 board for less than $200.00 >>>>> >>>>> http://store.digilentinc.com/pmodnic100-network-interface-controller/ >>>>> >>>>> It won't be low latency (the NIC has an SPI serial interface) but it >>>>> will teach concepts. >>>>> >>>>> Rob. >>>> >>>> Thanks. Is this the board you are referring to? >>>> http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/ >>>> >>>> >>>> If so, this board doesn't seem to have SPI (at least no listed in the >>>> description). Also, do you think this board has enough capacity (in >>>> terms of logic elements, etc.) to support a fairly complicated design >>>> like UDP/IP? >>> >>> What do you mean it doesn't have SPI? SPI is a simple shift register >>> interface which can *easily* be implemented in an FPGA (or MCU) using >>> the GPIOs. >>> >>> Do you mean ISP, in system programming? If it doesn't have ISP how do >>> you load your design? >>> >> >> It's a FPGA, you can add SPI easily, there are IPs for free to allow >> that to happen. >> >> In my post I was also going to mention the BASYS-3 board, I left it out >> because the Arty Board has a ton of memory available that this one >> doesn't but this on has a lot of switches and LED which can be handy. >> -- >> Cecil - k5nwa > > OK, thanks. I will check out both of them. What is the largest design you (or someone you know) have implemented on these boards? The Artix line seems to be lower end than Virtex line, so trying to get an idea if they can support somewhat complicated designs.No sure what "lower end" means in technical terms. I expect the Artix line of FPGAs will easily support somewhat complicated designs for reasonable values of "somewhat complicated". I suggest you not give much credence to marketing information and consider the chip specifications. For the most part the important issue is the LUT count. Otherwise the extra features are only useful if you need them. -- Rick C
Reply by ●August 29, 20162016-08-29
On 8/29/2016 4:30 PM, Cecil Bayona wrote:> > > On 8/29/2016 2:40 PM, PM X wrote: >> On Monday, August 29, 2016 at 11:38:27 AM UTC-7, Cecil Bayona wrote: >>> On 8/29/2016 1:32 PM, rickman wrote: >>>> On 8/29/2016 4:58 AM, PM X wrote: >>>>>> >>>>>> UDP/IP is much simpler the TCP/IP. It is commonly done in FPGAs. >>>>>> >>>>>> For example: >>>>>> >>>>>> http://www.fpga4fun.com/10BASE-T.html >>>>>> >>>>>> OK. It is only 10Base-T. But it's not that different than the >>>>>> 10GbE that >>>>>> we do. >>>>>> >>>>>> You can get a crappy NIC and Basys 3 Artix 7 board for less than >>>>>> $200.00 >>>>>> >>>>>> http://store.digilentinc.com/pmodnic100-network-interface-controller/ >>>>>> >>>>>> It won't be low latency (the NIC has an SPI serial interface) but it >>>>>> will teach concepts. >>>>>> >>>>>> Rob. >>>>> >>>>> Thanks. Is this the board you are referring to? >>>>> http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/ >>>>> >>>>> >>>>> >>>>> If so, this board doesn't seem to have SPI (at least no listed in the >>>>> description). Also, do you think this board has enough capacity (in >>>>> terms of logic elements, etc.) to support a fairly complicated design >>>>> like UDP/IP? >>>> >>>> What do you mean it doesn't have SPI? SPI is a simple shift register >>>> interface which can *easily* be implemented in an FPGA (or MCU) using >>>> the GPIOs. >>>> >>>> Do you mean ISP, in system programming? If it doesn't have ISP how do >>>> you load your design? >>>> >>> >>> It's a FPGA, you can add SPI easily, there are IPs for free to allow >>> that to happen. >>> >>> In my post I was also going to mention the BASYS-3 board, I left it out >>> because the Arty Board has a ton of memory available that this one >>> doesn't but this on has a lot of switches and LED which can be handy. >>> -- >>> Cecil - k5nwa >> >> OK, thanks. I will check out both of them. What is the largest design >> you (or someone you know) have implemented on these boards? The Artix >> line seems to be lower end than Virtex line, so trying to get an idea >> if they can support somewhat complicated designs. >> > Nothing Fancy, that is why in my earlier post I mentioned that I don't > have a lot of experience. I been working a 32 bit stack based CPU, but > it's a work in progress, I'm still sorting it out, it taken less than > 20% of the chip, but a stack CPU are rather simple compared to other > CPU's, when finished it should be pretty nice, most instructions take > one clock to execute, and it used packed instructions, 5 instructions to > a word fetch. Originally it was on a Lattice Brevia2, I am now > converting it to a Artix-7 board, but there is software involved too so > it's going slow and I'm learning as I go.Just a comment on your stack processor. I've done some design work with stack processors and read about a lot of designs. In my humble opinion, if you have multiple cycle instructions, you are doing it wrong. I don't want to steal the thread. If you care to discuss this we can start another thread. -- Rick C
