spartan 3 on 4 layers

Hi guys

I have just finished routing a simple board with a 208 pin qfp spartan
3. I have just used top and bottom layers and it is time to add the
power. I need 3.3v for all IO and the 1.2v and 2.5v for vccint and
vccaux. I have not routed any signal under the spartan on either layer
so I plan to use GND on 1 inner layer and 3.3 on the fourth layer with
an island of 1.2 or 2.5 under the spartan with 2.5 or 1.2 then on the
bottom layer.

Just wondering if anyone can see any holes in this idea.

thanks

colin

Colin,

Our SSO rules assume you have dedicated planes for Vccint, Vcco.  If you 
do not have both a power and a ground plane for each of these supplies, 
the SSO numbers must be reduced.  This also goes for simultaneously 
switching CLBs, and not just IOs.  We assume a power and ground plane 
(yes that would be four layers just for power) for low inductance on the 
Vccint/Vcco.

You might want to investigate the Point of Load concept (POL or POLA) 
from TI (US) and Belkin (Japan).

By placing power supplies directly at the load, the loop inductance is 
greatly reduced.

I have a SDRAM+2VP20 PCI pcb that has four layers, and operates very 
well.  Perhaps you pay more for a more capable power supply, but you pay 
less for the PCB.

Remember that V=-LdI/dt.  There is no way to reduce ground and Vcc 
bounce without reducing either the I (current switched by reducing the 
number of things switching), or reducing the L (indutance). The time 
(dt) is not something that can be changed (as in internal nodes switch 
time is fixed by process and design).

No amount of bypass caps will fix a bad pcb.

Austin

colin wrote:

> Hi guys
> 
> I have just finished routing a simple board with a 208 pin qfp spartan
> 3. I have just used top and bottom layers and it is time to add the
> power. I need 3.3v for all IO and the 1.2v and 2.5v for vccint and
> vccaux. I have not routed any signal under the spartan on either layer
> so I plan to use GND on 1 inner layer and 3.3 on the fourth layer with
> an island of 1.2 or 2.5 under the spartan with 2.5 or 1.2 then on the
> bottom layer.
> 
> Just wondering if anyone can see any holes in this idea.
> 
> thanks
> 
> colin

Colin,
It's hard to answer this question without knowing what the FPGA is doing. If
the I/Os are switching slowly, but the logic inside is going very fast, then
your Vccint supply is of paramount importance. For example, if all the slew
rates in the IOBs are set to slow, the 3.3V rail maybe doesn't need to be on
a plane. In fact a crappy Vcco can sometimes actually help EMI problems by
slowing the IO signals. I'd say that as you're using a PQ208, high speed
stuff isn't foremost in your mind.
When Xilinx say that 'all the supplies are recommended to be on a plane',
what I guess they mean is 'we tried it with all the supplies on a plane and
it met ALL our specs'. They're not saying other methodologies won't work,
especially if you're not trying to meet the fastest switching rates.
Although wire-wrap's probably a bad idea!
What you can do is what I think you're suggesting, have mini-planes for each
supply, sharing the PCB layer. If you can also get some 0402 caps on the
top-side (fpga-side) of the board very close to the pins, that'll help a
lot. With the package you're using just go for the biggest value X5R cap you
can get, 1uF probably, and route it on the top layer straight to the pins.
This takes the via inductance out of the equation. Don't worry about all
that 'use several different values to widen the resonance', that's probably
mumbo-jumbo in the real world, especially with a PQ208. There are too many
parasitics around to confuse the issue. Small package (=low inductance), big
capacitance is what you want!
The point-of-load supplies Austin mentions are a good idea, but don't bust a
gut getting them close to the FPGA, just make sure the supply rails have
very low AC impedance near the FPGA. So, lots of point-of-load decoupling
and lots of copper is what you need!
If I were you, I'd be optimistic. You're thinking about this, which gives
you a much, much higher chance of success than some folks...
Good luck, Syms.
p.s. More reading:-
http://www.sigcon.com/pubsIndex.htm
Look at 'Bypass Capacitors'.

"colin" <colin_toogood@yahoo.com> wrote in message
news:885a4a4a.0410130035.45941216@posting.google.com...
> Hi guys
>
> I have just finished routing a simple board with a 208 pin qfp spartan
> 3. I have just used top and bottom layers and it is time to add the
> power. I need 3.3v for all IO and the 1.2v and 2.5v for vccint and
> vccaux. I have not routed any signal under the spartan on either layer
> so I plan to use GND on 1 inner layer and 3.3 on the fourth layer with
> an island of 1.2 or 2.5 under the spartan with 2.5 or 1.2 then on the
> bottom layer.
>
> Just wondering if anyone can see any holes in this idea.
>
> thanks
>
> colin

Austin Lesea <austin@xilinx.com> wrote in message news:<ckjgil$5pe1@cliff.xsj.xilinx.com>...
> Colin,
> 
> Our SSO rules assume you have dedicated planes for Vccint, Vcco.  If you 
> do not have both a power and a ground plane for each of these supplies, 
> the SSO numbers must be reduced.  This also goes for simultaneously 
> switching CLBs, and not just IOs.  We assume a power and ground plane 
> (yes that would be four layers just for power) for low inductance on the 
> Vccint/Vcco.
> 
> You might want to investigate the Point of Load concept (POL or POLA) 
> from TI (US) and Belkin (Japan).
> 
> By placing power supplies directly at the load, the loop inductance is 
> greatly reduced.
> 
> I have a SDRAM+2VP20 PCI pcb that has four layers, and operates very 
> well.  Perhaps you pay more for a more capable power supply, but you pay 
> less for the PCB.
> 
> Remember that V=-LdI/dt.  There is no way to reduce ground and Vcc 
> bounce without reducing either the I (current switched by reducing the 
> number of things switching), or reducing the L (indutance). The time 
> (dt) is not something that can be changed (as in internal nodes switch 
> time is fixed by process and design).
> 
> No amount of bypass caps will fix a bad pcb.

This is a very curious statement. Bypass caps provide virtually all of
the high frequency current-they get recharged by power supply.
Granted, you need low impedance to recharge the caps before they are
used again, but the power supply is not supplying the fast edge
currents.

"Tom Seim" <soar2morrow@yahoo.com> wrote in message 
news:6c71b322.0410142059.6ff45611@posting.google.com...
> Austin Lesea <austin@xilinx.com> wrote in message
>> No amount of bypass caps will fix a bad pcb.
>
> This is a very curious statement. Bypass caps provide virtually all of
> the high frequency current-they get recharged by power supply.
> Granted, you need low impedance to recharge the caps before they are
> used again, but the power supply is not supplying the fast edge
> currents.
..but if your PCB puts too much inductance between the caps and the FPGA, 
this 'bad' PCB won't be fixed by merely adding more badly routed and 
positioned bypassing.
Cheers, Syms. 

Symon wrote:
> 
> "Tom Seim" <soar2morrow@yahoo.com> wrote in message
> news:6c71b322.0410142059.6ff45611@posting.google.com...
> > Austin Lesea <austin@xilinx.com> wrote in message
> >> No amount of bypass caps will fix a bad pcb.
> >
> > This is a very curious statement. Bypass caps provide virtually all of
> > the high frequency current-they get recharged by power supply.
> > Granted, you need low impedance to recharge the caps before they are
> > used again, but the power supply is not supplying the fast edge
> > currents.
> ..but if your PCB puts too much inductance between the caps and the FPGA,
> this 'bad' PCB won't be fixed by merely adding more badly routed and
> positioned bypassing.

I think he was addressing the comments about keeping the PSU near the
chips.  I have *never* heard anyone recommend that PSU placement would
affect the need for good PCB design.  The range of frequencies that PSU
selection or placement would affect is way below the range of freqencies
that would be affected by PCB layout.  I don't think anyone here is
talking about putting ceramic decoupling caps an inch from the chip
pins.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Tom,

There is no "C" in Ldi/dt.

If you can find out how varying a capacitance in any way changes the 
induced bounce (V=-Ldi/dt), let me know.

Bypass capacitance prevents rail collapse, but it does nothing to 
prevent ground bounce (it can actually make it worse, as there is more 
energy stored which makes di larger and dt faster).

Austin

Tom Seim wrote:
> Austin Lesea <austin@xilinx.com> wrote in message news:<ckjgil$5pe1@cliff.xsj.xilinx.com>...
> 
>>Colin,
>>
>>Our SSO rules assume you have dedicated planes for Vccint, Vcco.  If you 
>>do not have both a power and a ground plane for each of these supplies, 
>>the SSO numbers must be reduced.  This also goes for simultaneously 
>>switching CLBs, and not just IOs.  We assume a power and ground plane 
>>(yes that would be four layers just for power) for low inductance on the 
>>Vccint/Vcco.
>>
>>You might want to investigate the Point of Load concept (POL or POLA) 
>>from TI (US) and Belkin (Japan).
>>
>>By placing power supplies directly at the load, the loop inductance is 
>>greatly reduced.
>>
>>I have a SDRAM+2VP20 PCI pcb that has four layers, and operates very 
>>well.  Perhaps you pay more for a more capable power supply, but you pay 
>>less for the PCB.
>>
>>Remember that V=-LdI/dt.  There is no way to reduce ground and Vcc 
>>bounce without reducing either the I (current switched by reducing the 
>>number of things switching), or reducing the L (indutance). The time 
>>(dt) is not something that can be changed (as in internal nodes switch 
>>time is fixed by process and design).
>>
>>No amount of bypass caps will fix a bad pcb.
> 
> 
> This is a very curious statement. Bypass caps provide virtually all of
> the high frequency current-they get recharged by power supply.
> Granted, you need low impedance to recharge the caps before they are
> used again, but the power supply is not supplying the fast edge
> currents.

"Austin Lesea" <austin@xilinx.com> wrote in message
news:ckomo5$s21@cliff.xsj.xilinx.com...
> Tom,
>
> There is no "C" in Ldi/dt.
>
> If you can find out how varying a capacitance in any way changes the
> induced bounce (V=-Ldi/dt), let me know.
>
> Bypass capacitance prevents rail collapse, but it does nothing to
> prevent ground bounce (it can actually make it worse, as there is more
> energy stored which makes di larger and dt faster).
>
> Austin
[snip]

I think the point being made here is that bypass caps located where the
inductance between the caps and the chip is small, the i in di/dt *is*
significantly altered if the i being discussed is power/ground plane
inductance.

The regulator at the load should only help out if 1) the regulator has
extremely fast response or 2) the current demands fluctuate at very high
aplitudes at much lower frequencies.

The designer *must* keep in mind the effect of a sudden increase in current
on the total available charge from the bypass caps locally.  If the
step-increase in current deflates those bypass caps beyond the voltage
tolerance of the target device, very bad things will happen.  It's better to
overdesign the bypass caps (rather than relying on the minimum operating
voltage of the chip) because of other effects like induced jitter.

When the bypass caps do their job in the frequency range they're designed
for, the lower frequencies still need to be accommodated.  That's where the
regulator takes over.  With a response in the 10s of microseconds, a good
regulator won't have a problem delivering the change of current where the
bypass caps are starting to lose effectiveness.

If there are inexpensive regulators with 100s of nanoseconds respons time,
I'd be paying closer attention to a distributed power delivery approach.  I
took a quick look at a some LDO regulators which - while claiming to have
"fast transient response" - give no actual data on the recovery time.  Is it
worth a 500 mV dropout into 1.2V to use an LDO rather than a switcher far
from the chip with an appropriate bypassing scheme?

The "Point of Load" at ti.com comes up with a DC/DC switcher module where
"the transient response of the DC/DC converter has been
characterized using a load transient with a di/dt of 1 A/&#4294967295;s."  While this
appears to be a better spec than I originally figured (for available supply
voltages down to 3.3V, not 1.2V yet) the location could still easily be a
couple nanoseconds of board distance away (about 10"?) and not feel the
difference in the transient due to the di/dt of the power plane.

If there is a "new, better way" to power our transient-rich designs compared
to good - local - decoupling schemes, I'd be interested to read up.  As long
as decoupling is within 1/10 the wavelength of the capacitor's effective
frequency on a zero inductance plane, the capacitor will do it's job.  As
long as the capacitor is not degraded by the plane inductance between the
cap and the chip, the cap will do its job.  If a cap is marginalized by an
inductance, the cap will be less effective and some analysis may be
warranted.  The numbers whould be considered.

John_H wrote:
> 
> "Austin Lesea" <austin@xilinx.com> wrote in message
> news:ckomo5$s21@cliff.xsj.xilinx.com...
> > Tom,
> >
> > There is no "C" in Ldi/dt.
> >
> > If you can find out how varying a capacitance in any way changes the
> > induced bounce (V=-Ldi/dt), let me know.
> >
> > Bypass capacitance prevents rail collapse, but it does nothing to
> > prevent ground bounce (it can actually make it worse, as there is more
> > energy stored which makes di larger and dt faster).
> >
> > Austin
> [snip]
> 
> I think the point being made here is that bypass caps located where the
> inductance between the caps and the chip is small, the i in di/dt *is*
> significantly altered if the i being discussed is power/ground plane
> inductance.

The L di/dt issue is a red herring.  Every good engineer knows that *NO*
circuit is pure L or pure C or even pure R.  All circuits are a
combination of the three (hopefully linear) and what matters is the
resulting Z.  


> The regulator at the load should only help out if 1) the regulator has
> extremely fast response or 2) the current demands fluctuate at very high
> aplitudes at much lower frequencies.

NO regulator has enough speed to respond at the frequencies that power
planes address.  Even if they did, the required distance between the
regulator and the chip would add L (increasing the Z) to a point that
counters the feature.  


 
> When the bypass caps do their job in the frequency range they're designed
> for, the lower frequencies still need to be accommodated.  That's where the
> regulator takes over.  With a response in the 10s of microseconds, a good
> regulator won't have a problem delivering the change of current where the
> bypass caps are starting to lose effectiveness.

...snip..
 
> If there is a "new, better way" to power our transient-rich designs compared
> to good - local - decoupling schemes, I'd be interested to read up.  As long
> as decoupling is within 1/10 the wavelength of the capacitor's effective
> frequency on a zero inductance plane, the capacitor will do it's job.  As
> long as the capacitor is not degraded by the plane inductance between the
> cap and the chip, the cap will do its job.  If a cap is marginalized by an
> inductance, the cap will be less effective and some analysis may be
> warranted.  The numbers whould be considered.

You are preaching to the choir now!  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Rick,
I agree. As I said in another post in this thread, point-of-load supplies
are useful, but as long as you keep them on the board where they're used,
their position relative to the FPGA makes bugger all difference. They're low
enough in area/height/power wastage these days to place in the bits of pcb
'tundra' you often get between connectors and the like!
Cheers, Syms.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:416F6DB9.9DBF780F@yahoo.com...
> Symon wrote:
>
> I think he was addressing the comments about keeping the PSU near the
> chips.  I have *never* heard anyone recommend that PSU placement would
> affect the need for good PCB design.  The range of frequencies that PSU
> selection or placement would affect is way below the range of freqencies
> that would be affected by PCB layout.