spartan 3 on 4 layers

Hal Murray wrote:

>>Our SSO rules assume you have dedicated planes for Vccint, Vcco.  If you 
>>do not have both a power and a ground plane for each of these supplies, 
>>the SSO numbers must be reduced.  This also goes for simultaneously 
>>switching CLBs, and not just IOs.  We assume a power and ground plane 
>>(yes that would be four layers just for power) for low inductance on the 
>>Vccint/Vcco.

> That seems reasonable, but it's awful short on specifics.

> How big does the plane have to be?  Are you assuming power/gnd pairs?
> If so, what spacing between the pairs?  Which plane/pair needs
> to be closest to the chip?

Inductance should also go down with the thickness of the copper,
though at some point you run into the skin effect.
Thicker copper might be cheaper than more layers.

-- glen

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:cl3k1f$kdm$1@gnus01.u.washington.edu...

> Inductance should also go down with the thickness of the copper,
> though at some point you run into the skin effect.
> Thicker copper might be cheaper than more layers.
>
> -- glen
Glen,
Good point, but sometimes thicker copper can be a mixed blessing, the
etching process can screw up if the copper's too thick. Thinner copper
allows narrower tracks. This can let you squeeze your routing together, to
get wide tracks to where you need it. Important if you're routing power on a
routing layer. On the other hand, thick copper helps heat transfer.
Another classic engineering compromise!
Best, Syms.

Austin wrote:
> 
> SSO guidelines are on page 23 of:
> 
> http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
> 
 Except for the leaded S3 packages {VQ/TQ/PQ}, which are still
conspicuously absent from table 23.

 Other table 23 oddities:

 1)  Why are the SSO pin limits for those spiffy current mode
   differential drivers so low, nearly the same as for the high
   drive single ended I/O standards?

     Answer Record 19972 still says "Because the Spartan-3 LVDS
   driver is very balanced, its switching causes a negligible
   amount of transient current. As a result, SSOs are not a problem."

 2)  Why are the table 23 SSO limits for the older voltage-mode
   differential output drivers {LVPECL,BLVDS} identical to those
   of the newer current-mode drivers {LVDS,LDT,RSDS} ? 

 3)  Why do the input-only differential parallel DCI standards
   show up in the SSO table?


Brian

I wrote:

>>Inductance should also go down with the thickness of the copper,
>>though at some point you run into the skin effect.
>>Thicker copper might be cheaper than more layers.

Symon wrote:

> Good point, but sometimes thicker copper can be a mixed blessing, the
> etching process can screw up if the copper's too thick. Thinner copper
> allows narrower tracks. This can let you squeeze your routing together, to
> get wide tracks to where you need it. Important if you're routing power on a
> routing layer. On the other hand, thick copper helps heat transfer.
> Another classic engineering compromise!

I was suggesting it for the power and ground planes, but I don't
know which combinations of mixing different thicknesses are allowed.

Is a four layer board built from two 2-layer boards etched separately
and then put together with an insulation layer in between?  It might
be that both sides of the separate boards would have to be the same.

-- glen

On Tue, 19 Oct 2004 12:06:21 -0700, glen herrmannsfeldt
<gah@ugcs.caltech.edu> wrote:

>
>I wrote:
>
>>>Inductance should also go down with the thickness of the copper,
>>>though at some point you run into the skin effect.
>>>Thicker copper might be cheaper than more layers.
>
>Symon wrote:
>
>> Good point, but sometimes thicker copper can be a mixed blessing, the
>> etching process can screw up if the copper's too thick. Thinner copper
>> allows narrower tracks. This can let you squeeze your routing together, to
>> get wide tracks to where you need it. Important if you're routing power on a
>> routing layer. On the other hand, thick copper helps heat transfer.
>> Another classic engineering compromise!
>
>I was suggesting it for the power and ground planes, but I don't
>know which combinations of mixing different thicknesses are allowed.
>
>Is a four layer board built from two 2-layer boards etched separately

They are called "cores".

>and then put together with an insulation layer in between?

That is called "prepreg".

>  It might
>be that both sides of the separate boards would have to be the same.

That is usually the case, although it is possible to build up copper
thickness by plating e.g. the outer layers.

Regards,
Allan

"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in
message news:k0qan0pj35a93gnv0muhca7h13ivfntl62@4ax.com...
>
> They are called "cores".
>
> >and then put together with an insulation layer in between?
>
> That is called "prepreg".
>
> >  It might
> >be that both sides of the separate boards would have to be the same.
>
> That is usually the case, although it is possible to build up copper
> thickness by plating e.g. the outer layers.
>
> Regards,
> Allan
Glen, Allan,
For a four layer board, I think it is possible to have a core, with prepreg
on either side, overlaid with foil for the outer copper layers. I use
something like this in my microvia boards, the prepreg is laserable.
Probably more expensive though.
As for whether thicker copper is useful on layers inside the board for SI
reasons, I expect the limiting factor is the via + track + lead frame
inductance to the pad, rather than the plane inductance. Good for thermal
reasons though.
Cheers, Syms.

Hi Brian,
Comments:-
"Brian Davis" <brimdavis@aol.com> wrote in message
news:a528ffe0.0410191100.7b2c6935@posting.google.com...
> Austin wrote:
> >
> > SSO guidelines are on page 23 of:
> >
> > http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
> >
>  Except for the leaded S3 packages {VQ/TQ/PQ}, which are still
> conspicuously absent from table 23.
>

That's because the lead frame has buggered your SI before you've even
started your PCB.

>  Other table 23 oddities:
>
>  1)  Why are the SSO pin limits for those spiffy current mode
>    differential drivers so low, nearly the same as for the high
>    drive single ended I/O standards?
>
>      Answer Record 19972 still says "Because the Spartan-3 LVDS
>    driver is very balanced, its switching causes a negligible
>    amount of transient current. As a result, SSOs are not a problem."
>
>  2)  Why are the table 23 SSO limits for the older voltage-mode
>    differential output drivers {LVPECL,BLVDS} identical to those
>    of the newer current-mode drivers {LVDS,LDT,RSDS} ?
>

The idea is that if the voltage mode drivers switch simultaneously in
opposite directions, the current through the Vcco pins stays constant, so
the lead/trace inductance doesn't screw things up.

>  3)  Why do the input-only differential parallel DCI standards
>    show up in the SSO table?
>
>
> Brian

Dunno!

Symon wrote:

(after I asked about thicker copper on some layers)

> For a four layer board, I think it is possible to have a core, with prepreg
> on either side, overlaid with foil for the outer copper layers. I use
> something like this in my microvia boards, the prepreg is laserable.
> Probably more expensive though.
> As for whether thicker copper is useful on layers inside the board for SI
> reasons, I expect the limiting factor is the via + track + lead frame
> inductance to the pad, rather than the plane inductance. Good for thermal
> reasons though.

The suggestion was to improve the ground plane by making it
thicker.   To reduce via inductance you need as many of them
as you can get.  (Inductors in parallel.)   The OP wanted a four
layer board instead of following the suggested two ground and
two power planes.

-- glen

Brian,

See below,

Austin

Brian Davis wrote:
> Austin wrote:
> 
>>SSO guidelines are on page 23 of:
>>
>>http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
>>
> 
>  Except for the leaded S3 packages {VQ/TQ/PQ}, which are still
> conspicuously absent from table 23.
> 
>  Other table 23 oddities:
> 
>  1)  Why are the SSO pin limits for those spiffy current mode
>    differential drivers so low, nearly the same as for the high
>    drive single ended I/O standards?
> 
>      Answer Record 19972 still says "Because the Spartan-3 LVDS
>    driver is very balanced, its switching causes a negligible
>    amount of transient current. As a result, SSOs are not a problem."

LVDS is a low current driver, but the LVPECL is two single ended drivers 
with external resistors, so it has significant current.

Even LVDS has a restriction, but not nearly that of a larger driver 
(more current).  Unless I am missing something?


> 
>  2)  Why are the table 23 SSO limits for the older voltage-mode
>    differential output drivers {LVPECL,BLVDS} identical to those
>    of the newer current-mode drivers {LVDS,LDT,RSDS} ? 

??? I'll have to ask Steve K.

> 
>  3)  Why do the input-only differential parallel DCI standards
>    show up in the SSO table?

Because they draw current for the parallel termiantion, and the 
restriction is for current drain on the Vcco/Gnd pins in the bank.

> 
> 
> Brian

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:cl3t0g$qob$1@gnus01.u.washington.edu...
>
> The suggestion was to improve the ground plane by making it
> thicker.   To reduce via inductance you need as many of them
> as you can get.  (Inductors in parallel.)   The OP wanted a four
> layer board instead of following the suggested two ground and
> two power planes.
>
I just realised, making it thicker will only reduce its resistance. Its
inductance won't change. The inductance is determined by the loop area of
the current path. Think about it, when you calculate the inductance of a
coil, you don't need to know the wire diameter, just the diameter and number
of turns.
Best, Syms.