spartan 3 on 4 layers

Austin,
PCB ground bounce? But this thread is about not having PCB power planes.
No-one's suggesting doing without a ground plane. That's your main (only!)
weapon against ground bounce. The loop-inductance you're taking about that
carries the return current is then between the FPGA and it's decoupling
capacitors. The ground plane ensures the power supply doesn't bounce
relative to the decoupled supply at the FPGA.
If you're talking about ground bounce on the silicon, then all we PCB
designers can do is firmly bolt down the ground pins to the PCB ground
plane. A power plane, or lack thereof, isn't gonna affect ground bounce
after that.
Also, when you say in a previous post 'If you do not have both a power and a
ground plane for each of these supplies, the SSO numbers must be reduced.',
I'd disagree. You probably must have a ground plane, but throwing separate
layers at supplies for Vcco, Vccint, Vccaux, Rocket I/O supplies is a little
excessive! It's easier to use this methodology, and certainly easier for
Xilinx to support, but you can get as good results by using one or two
layers to share supplies locally at the FPGA. You can also use this layer
for other things away from the FPGA. To do this, your decoupling must be
good at the FPGA, and the connection between the supply and the local plane
must be able to supply the current needed.
You're also, IMHO, better off having multiple ground planes, and routing the
power.
Finally, I'd be interested in how increasing bypass capacitance can make
ground bounce worse in the same system, especially one with a ground plane?
More energy stored? di larger? dt faster? What?
Cheers, Syms.
"Austin Lesea" <austin@xilinx.com> wrote in message
news:ckomo5$s21@cliff.xsj.xilinx.com...
> Tom,
>
> There is no "C" in Ldi/dt.
>
> If you can find out how varying a capacitance in any way changes the
> induced bounce (V=-Ldi/dt), let me know.
>
> Bypass capacitance prevents rail collapse, but it does nothing to
> prevent ground bounce (it can actually make it worse, as there is more
> energy stored which makes di larger and dt faster).
>
> Austin
>

Austin,
PCB ground bounce? But this thread is about not having PCB power planes.
No-one's suggesting doing without a ground plane. That's your main (only!)
weapon against ground bounce. The loop-inductance you're taking about that
carries the return current is then between the FPGA and it's decoupling
capacitors. The ground plane ensures the power supply doesn't bounce
relative to the decoupled supply at the FPGA.
If you're talking about ground bounce on the silicon, then all we PCB
designers can do is firmly bolt down the ground pins to the PCB ground
plane. A power plane, or lack thereof, isn't gonna affect ground bounce
after that.
Also, when you say in a previous post 'If you do not have both a power and a
ground plane for each of these supplies, the SSO numbers must be reduced.',
I'd disagree. You probably must have a ground plane, but throwing separate
layers at supplies for Vcco, Vccint, Vccaux, Rocket I/O supplies is a little
excessive! It's easier to use this methodology, and certainly easier for
Xilinx to support, but you can get as good results by using one or two
layers to share supplies locally at the FPGA. You can also use this layer
for other things away from the FPGA. To do this, your decoupling must be
good at the FPGA, and the connection between the supply and the local plane
must be able to supply the current needed.
You're also, IMHO, better off having multiple ground planes, and routing the
power. Or use ground flood to help.
Finally, I'd be interested in how increasing bypass capacitance can make
ground bounce worse in the same system, especially one with a ground plane?
More energy stored? di larger? dt faster? What?
Cheers, Syms.
"Austin Lesea" <austin@xilinx.com> wrote in message
news:ckomo5$s21@cliff.xsj.xilinx.com...
> Tom,
>
> There is no "C" in Ldi/dt.
>
> If you can find out how varying a capacitance in any way changes the
> induced bounce (V=-Ldi/dt), let me know.
>
> Bypass capacitance prevents rail collapse, but it does nothing to
> prevent ground bounce (it can actually make it worse, as there is more
> energy stored which makes di larger and dt faster).
>
> Austin
>

John,

See comments below,

Austin


> [snip]
> 
> I think the point being made here is that bypass caps located where the
> inductance between the caps and the chip is small, the i in di/dt *is*
> significantly altered if the i being discussed is power/ground plane
> inductance.

Actually, my point is this: given some bypass arrangement, the ground 
bounce does not vary if you suddenly make all the byapssing 10X better 
(ie better caps, more farads).  In fact, bounce may get worse because 
the rails are not collapsing (anymore) externally.

> 
> The regulator at the load should only help out if 1) the regulator has
> extremely fast response or 2) the current demands fluctuate at very high
> aplitudes at much lower frequencies.

Agreed.  On chip, the current demand is almost instant.  By the time the 
local capacitance on die is exhausted, and the caps in the package are 
out of charge, and the immediate external bypass caps have also given up 
their electrons, the time of the current profile has been stretched.  If 
a regulator is fast enough, it can help.  If it is too slow, it can't.

The PCI/SDRAM card I have with the POL ultra-fast transient regulators 
was able to use 4 layers.  Never seen anything less than 8 layers used 
before.  Pretty clever designers for that PDS.

-snip-

> The "Point of Load" at ti.com comes up with a DC/DC switcher module where
> "the transient response of the DC/DC converter has been
> characterized using a load transient with a di/dt of 1 A/�s."  While this
> appears to be a better spec than I originally figured (for available supply
> voltages down to 3.3V, not 1.2V yet) the location could still easily be a
> couple nanoseconds of board distance away (about 10"?) and not feel the
> difference in the transient due to the di/dt of the power plane.

I believe they have all the way down to 1.0 volt available now.  Check 
with your TI disti.  Belnix is adjustable with a resistor.

http://www.belnix.co.jp  (most of the literature is in Japanese, and I 
have received some recent English translations, but I am still at a 
disadvantage here....)

http://focus.ti.com/docs/pr/pressrelease.jhtml?prelId=sc04126

> 
> If there is a "new, better way" to power our transient-rich designs compared
> to good - local - decoupling schemes, I'd be interested to read up.  As long
> as decoupling is within 1/10 the wavelength of the capacitor's effective
> frequency on a zero inductance plane, the capacitor will do it's job.  As
> long as the capacitor is not degraded by the plane inductance between the
> cap and the chip, the cap will do its job.  If a cap is marginalized by an
> inductance, the cap will be less effective and some analysis may be
> warranted.  The numbers whould be considered.

Agree on all of the above.

The Belnix POL supply has a 50 mV  MAX droop for a 5 ampere load change 
(step, instant load change).  Looks like it never even saw the load 
change, except the IR drop happens and you see 50 mV change.  They talk 
about a ~100 ns time to go from 0 amperes, to supplying 5 amperes with 
no overshoot or ringing of the output (beyond the normal switching noise 
and the IR drop of 50 mV).

Initially, I was a non-believer, like you.  Basic rules were separate 
planes, minimize inductance, maximize bypass, etc.  1/10 wavelength back 
of the envelope rules, etc.  Then I saw a 4 layer pcb with a POL 
regulator (actually, two, one for core, and one for IO) and very few 
bypass caps.  I had never seen a working 4 layer pcb prior to that with 
PCI AND SDRAM on a 2VP20 (let alone one without a lot of caps).  Just 
too much current needs to be switched for BOTH PCI and SDRAM, and the 
only other solution I had seen were two planes for Vccint, and two 
planes for Vcco, plus a lot of bypass caps (one per power ground pin pair).

Perhaps we are both over simplifying the problem?  Perhaps is it more 
like a power transfer problem over a 2-D transmission line:   the longer 
the line, the worse the problem?  By shortening the line to less than 1" 
(25.4mm), the POL concept is a better solution?  The output impedance of 
the power supply (an active and complex value) is reflected to the load 
and is kept at a much lower magnitude, which causes much less voltage 
fluctuation?

Rick,
I agree. As I said in another post in this thread, point-of-load supplies
are useful, but as long as you keep them on the board where they're used,
their position relative to the FPGA makes bugger all difference. They're low
enough in area/height/power wastage these days to place in the bits of pcb
'tundra' you often get between connectors and the like!
Cheers, Syms.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:416F6DB9.9DBF780F@yahoo.com...
> Symon wrote:
>
> I think he was addressing the comments about keeping the PSU near the
> chips.  I have *never* heard anyone recommend that PSU placement would
> affect the need for good PCB design.  The range of frequencies that PSU
> selection or placement would affect is way below the range of freqencies
> that would be affected by PCB layout.

Austin,
PCB ground bounce? But this thread is about not having PCB power planes.
No-one's suggesting doing without a ground plane. That's the main (only!)
weapon against ground bounce. The loop-inductance you're taking about that
carries the return current is then between the FPGA and it's decoupling
capacitors. The ground plane ensures the power supply doesn't bounce
relative to the decoupled supply at the FPGA.
If you're talking about ground bounce on the silicon, then all we PCB
designers can do is firmly bolt down the ground pins to the PCB ground
plane. A power plane, or lack thereof, isn't gonna affect ground bounce
after that.
Also, when you say in a previous post 'If you do not have both a power and a
ground plane for each of these supplies, the SSO numbers must be reduced.',
I'd disagree. You probably must have a ground plane, but throwing separate
layers at supplies for Vcco, Vccint, Vccaux, Rocket I/O supplies is a little
excessive! It's easier to use this methodology, and certainly easier for
Xilinx to support, but you can get as good results by using one or two
layers to share supplies locally at the FPGA. You can also use this layer
for other things away from the FPGA. To do this, your decoupling must be
good at the FPGA, and the connection between the supply and the local plane
must be able to supply the current needed.
You're also, IMHO, better off having multiple ground planes, and routing the
power.
Finally, I'd be interested in how increasing bypass capacitance can make
ground bounce worse in the same system, especially one with a ground plane?
More energy stored? di larger? dt faster? What?
Cheers, Syms.
"Austin Lesea" <austin@xilinx.com> wrote in message
news:ckomo5$s21@cliff.xsj.xilinx.com...
> Tom,
>
> There is no "C" in Ldi/dt.
>
> If you can find out how varying a capacitance in any way changes the
> induced bounce (V=-Ldi/dt), let me know.
>
> Bypass capacitance prevents rail collapse, but it does nothing to
> prevent ground bounce (it can actually make it worse, as there is more
> energy stored which makes di larger and dt faster).
>
> Austin
>

Symon,

Answers below,

Austin

Symon wrote:
> Austin,
> PCB ground bounce? But this thread is about not having PCB power planes.

It was about number of layers.  A ground plane is a layer.

> No-one's suggesting doing without a ground plane. That's the main (only!)
> weapon against ground bounce. The loop-inductance you're taking about that
> carries the return current is then between the FPGA and it's decoupling
> capacitors. The ground plane ensures the power supply doesn't bounce
> relative to the decoupled supply at the FPGA.

The ground L is the bounce in the ground plane.  The Vcc plane L is the 
bounce in the Vcc.

> If you're talking about ground bounce on the silicon, then all we PCB
> designers can do is firmly bolt down the ground pins to the PCB ground
> plane. A power plane, or lack thereof, isn't gonna affect ground bounce
> after that.
> Also, when you say in a previous post 'If you do not have both a power and a
> ground plane for each of these supplies, the SSO numbers must be reduced.',
> I'd disagree. You probably must have a ground plane, but throwing separate
> layers at supplies for Vcco, Vccint, Vccaux, Rocket I/O supplies is a little
> excessive!

I said a pair of planes for each high current switching supply, namely a 
Vccint/Gnd pair, and a Vcco/Gnd pair.  That makes four layers.  The dual 
grounds are required to reduce the ground return inductance to something 
that is reasonable.  And the vcc loop inductance.  Both.

  It's easier to use this methodology, and certainly easier for
> Xilinx to support, but you can get as good results by using one or two
> layers to share supplies locally at the FPGA.

I disagree.  Looking at those that succeed, vs. those who have issues, I 
see those that followed our recommendations a much happier bunch.

We take our recommendations very seriously.  We are not out to minimize 
our support, but rather to maximize our customers' successes (and our 
own in the process).  To suggest a marginal power distribution system is 
just not good business!  Why would we suggest that a customer 'play 
around' when we and our disti's have already run all the simulations, 
and built numerous verification, characterization, and demo pcbs to 
prove what works, and what does not work?

Anyone who thinks they know better how to use our chip might get lucky, 
but often is not.  Why would anyone think that they know more than we do 
about something they did not design?  Surprisingly, many do think that 
they know more, and as a consequence are sometimes terribly disappointed.

For the introduction of V4, we had a 1Gb/s LVDS networking pcb ready to 
demo, and a memory interfaces pcb ready to demo.  Those are two of the 
largest applications problems our customers face today - fast IOs and 
fast memories.  If we don't know how to make it work, how would that 
make a customer feel?

I always read how a vendor suggests using their device.

The use of the POL supplies is an experiment to validate a concept.  I 
wouldn't go to product until I had proven it works (if it was my job).

The same goes for using only four layers, or traces to Vcco, etc.

  You can also use this layer
> for other things away from the FPGA. To do this, your decoupling must be
> good at the FPGA, and the connection between the supply and the local plane
> must be able to supply the current needed.
> You're also, IMHO, better off having multiple ground planes, and routing the
> power.

Yes, ground is all important (more so than the Vcc's), and Vcc 'planes' 
may sometimes just be routed.  It depends again on the switched currents.

> Finally, I'd be interested in how increasing bypass capacitance can make
> ground bounce worse in the same system, especially one with a ground plane?
> More energy stored?

Yes, the rails don't collapse.

  di larger?

Yes, the source impedance is lower.

  dt faster?

Yes, lower source impedance also leads to faster transients.

Lastly, we had a case where the vias from the bypass caps where wired 
such that the L from the cap to the plane was the largest element (not 
hard to do, one tiny via each end, at the end of a flag of trace to the 
chip cap).  Adding caps directly across the existing cap did absolutely 
nothing.  One might conclude that the bypassing wasn't doing anything. 
But really, the L to the caps was so bad, that the caps were not doing 
anything.  Little things count.

Had to tell the pcb layout person to get the L out of there! (excuse the 
pun - again)

More comments:-
"Austin Lesea" <austin@xilinx.com> wrote in message
news:ckpd8h$rn2@cliff.xsj.xilinx.com...
> Symon,
>
> Answers below,
>
> Austin
>
> Symon wrote:
> > Austin,
> > PCB ground bounce? But this thread is about not having PCB power planes.
>
> It was about number of layers.  A ground plane is a layer.
>

Go back and read the OP. He had a ground plane, he wanted to know if he
could get away with routing the power separately. Yes he can! Especially
with a PQ208 which has a lead frame made of little inductors on every pin! I
hope you Xilinx boys have encapsulated some bypass caps in there somewhere!

> > No-one's suggesting doing without a ground plane. That's the main
(only!)
> > weapon against ground bounce. The loop-inductance you're taking about
that
> > carries the return current is then between the FPGA and it's decoupling
> > capacitors. The ground plane ensures the power supply doesn't bounce
> > relative to the decoupled supply at the FPGA.
>
> The ground L is the bounce in the ground plane.  The Vcc plane L is the
> bounce in the Vcc.
>

Assuming the ground balls/pins are connected straight to the ground plane
and if the Vcc balls/pins are coupled tightly to the ground plane via
sufficient decoupling capacitors and enough low inductance copper
track/local plane, you don't need a Vcc plane that traverses the whole
board. The current loop is between the ground plane, the FPGA, the bypass
cap. One plane can't bounce without the other if the bypass caps nail them
together!

> > If you're talking about ground bounce on the silicon, then all we PCB
> > designers can do is firmly bolt down the ground pins to the PCB ground
> > plane. A power plane, or lack thereof, isn't gonna affect ground bounce
> > after that.
> > Also, when you say in a previous post 'If you do not have both a power
and a
> > ground plane for each of these supplies, the SSO numbers must be
reduced.',
> > I'd disagree. You probably must have a ground plane, but throwing
separate
> > layers at supplies for Vcco, Vccint, Vccaux, Rocket I/O supplies is a
little
> > excessive!
>
> I said a pair of planes for each high current switching supply, namely a
> Vccint/Gnd pair, and a Vcco/Gnd pair.  That makes four layers.  The dual
> grounds are required to reduce the ground return inductance to something
> that is reasonable.  And the vcc loop inductance.  Both.
>

Not necessary. The ground layer is important, as I said later more ground
planes are good. But big planes for Vcco and Vccint are NOT necessary. Just
low inductance from the bypass caps to the FPGA power pins/balls.

>   It's easier to use this methodology, and certainly easier for
> > Xilinx to support, but you can get as good results by using one or two
> > layers to share supplies locally at the FPGA.
>
> I disagree.  Looking at those that succeed, vs. those who have issues, I
> see those that followed our recommendations a much happier bunch.
>

Maybe you could come up with better recommendations, then your happy bunch
might get happier and richer from the money they save on PCBs!

> We take our recommendations very seriously.  We are not out to minimize
> our support, but rather to maximize our customers' successes (and our
> own in the process).  To suggest a marginal power distribution system is
> just not good business!  Why would we suggest that a customer 'play
> around' when we and our disti's have already run all the simulations,
> and built numerous verification, characterization, and demo pcbs to
> prove what works, and what does not work?

Fair enough. I'm sure this is true.

>
> Anyone who thinks they know better how to use our chip might get lucky,
> but often is not.  Why would anyone think that they know more than we do
> about something they did not design?  Surprisingly, many do think that
> they know more, and as a consequence are sometimes terribly disappointed.
>

Deep breath! I can see why you sometimes rile up Rickman! ;-) Anyway, I
count myself as someone who does know better how to use the chip in this
case, at least better than XAPP623, and I have plenty of boards to back it
up. When you get lucky every time, there's another word for it. I'm not
saying it's easy, but it's possible, and I save my company a lot of money on
PCBs by using fewer layers, fewer bypass caps, and squeezing extra
functionality onto the board. What I'm trying to do with my posts here is
help other folks understand that what Xilinx says is only one way to do it;
other ways work, and work very well. Don't get me wrong, I think Xilinx does
an excellent job, especially at support. Your recommendations enable someone
with little PCB design expertise to get it right first time. Sometimes
though, we non-Xilinx 'gentiles' can do good stuff too!

> For the introduction of V4, we had a 1Gb/s LVDS networking pcb ready to
> demo, and a memory interfaces pcb ready to demo.  Those are two of the
> largest applications problems our customers face today - fast IOs and
> fast memories.  If we don't know how to make it work, how would that
> make a customer feel?
>
> I always read how a vendor suggests using their device.
>

We agree on this!

> The use of the POL supplies is an experiment to validate a concept.  I
> wouldn't go to product until I had proven it works (if it was my job).
>
> The same goes for using only four layers, or traces to Vcco, etc.
>
>   You can also use this layer
> > for other things away from the FPGA. To do this, your decoupling must be
> > good at the FPGA, and the connection between the supply and the local
plane
> > must be able to supply the current needed.
> > You're also, IMHO, better off having multiple ground planes, and routing
the
> > power.
>
> Yes, ground is all important (more so than the Vcc's), and Vcc 'planes'
> may sometimes just be routed.  It depends again on the switched currents.
>

OK, so now we agree that a routed/local planed Vcc works? You seem to
flip-flop more than a Democrat nominee! ;-) Again we agree, local plane/
routed can Vcc work fine.

> > Finally, I'd be interested in how increasing bypass capacitance can make
> > ground bounce worse in the same system, especially one with a ground
plane?
> > More energy stored?
>
> Yes, the rails don't collapse.

But if the rails collapse, ground bounce is the least of your worries. Your
design is already dead.

>
>   di larger?
>
> Yes, the source impedance is lower.
>
>   dt faster?
>
> Yes, lower source impedance also leads to faster transients.
>

At these high frequencies, the capacitor package size (= inductance) is the
thing that dominates the source impedance. Not the capacitance. Look at the
manufacturers data sheets. Download this and look for yourself
http://www.murata.com/designlib/mcsil.html . Above 50MHz an X5R 0402 cap has
the same impedance whether it's 56nF or 470nF. The ground bounce problem is
solely a result of poor coupling between the ground plane and the FPGA.

> Lastly, we had a case where the vias from the bypass caps where wired
> such that the L from the cap to the plane was the largest element (not
> hard to do, one tiny via each end, at the end of a flag of trace to the
> chip cap).  Adding caps directly across the existing cap did absolutely
> nothing.  One might conclude that the bypassing wasn't doing anything.
> But really, the L to the caps was so bad, that the caps were not doing
> anything.  Little things count.
>
> Had to tell the pcb layout person to get the L out of there! (excuse the
> pun - again)

Of course, very good point. It's a constant fight against the PCB routing
tool to prevent it stripping out extra vias I add to decrease impedance.
Ah, Austin, I enjoy these chats. Even when I C your terrible puns!
Write back soon mate,
Syms. ;-)

>Our SSO rules assume you have dedicated planes for Vccint, Vcco.  If you 
>do not have both a power and a ground plane for each of these supplies, 
>the SSO numbers must be reduced.  This also goes for simultaneously 
>switching CLBs, and not just IOs.  We assume a power and ground plane 
>(yes that would be four layers just for power) for low inductance on the 
>Vccint/Vcco.

That seems reasonable, but it's awful short on specifics.

How big does the plane have to be?  Are you assuming power/gnd pairs?
If so, what spacing between the pairs?  Which plane/pair needs
to be closest to the chip?

Is there a procedure for computing the SSO rules given non-optimal
power planes?

Wise-ass mode would be:
  What page of the data sheet describes the details?


Let's go at it from the other direction.  What are the chances of
making a solid PCI card on a 4 layer board?  Assume a TQFP-208
package and assume that the PCI side is the major SSO problem
and that the routing on the non-PCI signals is easy.


I haven't done it, but I think you can get a reasonable layout
in 4 layers with a TQFP package.  I'm assuming that the routing
to the signal pins from the rest of the design is easy.
(That's "reasonable" to my imagination/eyeball.  Reality might
be totally different.)

The idea is that the top/bottom layers under the chip are not
needed for routing so you can fill them with copper to get
a tiny plane.  It's probably not big enough to do much good,
as a plane, but it will be a solid connection for all the
appropriate power/gnd pins and bypass caps.

It would be interesting to see how good that chunk of plane
approach is compared to placing bypass caps right next to each
pair of power/ground pins (with tight routing and fat traces).


I've got a cheap modem PCI card handy.  Looks like it's only
2 layers.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.

Hal,

For specifics, please read:

http://www.support.xilinx.com/products/design_resources/highspeed_design/resource/si_power.htm

SSO guidelines are on page 23 of:

http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf

Austin


Hal Murray wrote:
>>Our SSO rules assume you have dedicated planes for Vccint, Vcco.  If you 
>>do not have both a power and a ground plane for each of these supplies, 
>>the SSO numbers must be reduced.  This also goes for simultaneously 
>>switching CLBs, and not just IOs.  We assume a power and ground plane 
>>(yes that would be four layers just for power) for low inductance on the 
>>Vccint/Vcco.
> 
> 
> That seems reasonable, but it's awful short on specifics.
> 
> How big does the plane have to be?  Are you assuming power/gnd pairs?
> If so, what spacing between the pairs?  Which plane/pair needs
> to be closest to the chip?
> 
> Is there a procedure for computing the SSO rules given non-optimal
> power planes?
> 
> Wise-ass mode would be:
>   What page of the data sheet describes the details?
> 
> 
> Let's go at it from the other direction.  What are the chances of
> making a solid PCI card on a 4 layer board?  Assume a TQFP-208
> package and assume that the PCI side is the major SSO problem
> and that the routing on the non-PCI signals is easy.
> 
> 
> I haven't done it, but I think you can get a reasonable layout
> in 4 layers with a TQFP package.  I'm assuming that the routing
> to the signal pins from the rest of the design is easy.
> (That's "reasonable" to my imagination/eyeball.  Reality might
> be totally different.)
> 
> The idea is that the top/bottom layers under the chip are not
> needed for routing so you can fill them with copper to get
> a tiny plane.  It's probably not big enough to do much good,
> as a plane, but it will be a solid connection for all the
> appropriate power/gnd pins and bypass caps.
> 
> It would be interesting to see how good that chunk of plane
> approach is compared to placing bypass caps right next to each
> pair of power/ground pins (with tight routing and fat traces).
> 
> 
> I've got a cheap modem PCI card handy.  Looks like it's only
> 2 layers.
> 

"Hal Murray" <hmurray@suespammers.org> wrote in message
news:t7-dnUVydsUKXOncRVn-oQ@megapath.net...
> That seems reasonable, but it's awful short on specifics.
>
> How big does the plane have to be?  Are you assuming power/gnd pairs?
> If so, what spacing between the pairs?  Which plane/pair needs
> to be closest to the chip?
>
> Is there a procedure for computing the SSO rules given non-optimal
> power planes?
>
> Wise-ass mode would be:
>   What page of the data sheet describes the details?
>
>
> Let's go at it from the other direction.  What are the chances of
> making a solid PCI card on a 4 layer board?  Assume a TQFP-208
> package and assume that the PCI side is the major SSO problem
> and that the routing on the non-PCI signals is easy.
>
>
> I haven't done it, but I think you can get a reasonable layout
> in 4 layers with a TQFP package.  I'm assuming that the routing
> to the signal pins from the rest of the design is easy.
> (That's "reasonable" to my imagination/eyeball.  Reality might
> be totally different.)
>
> The idea is that the top/bottom layers under the chip are not
> needed for routing so you can fill them with copper to get
> a tiny plane.  It's probably not big enough to do much good,
> as a plane, but it will be a solid connection for all the
> appropriate power/gnd pins and bypass caps.
>
> It would be interesting to see how good that chunk of plane
> approach is compared to placing bypass caps right next to each
> pair of power/ground pins (with tight routing and fat traces).
>
>
> I've got a cheap modem PCI card handy.  Looks like it's only
> 2 layers.
>
Hal,
For this PCI card, I think the I/O will be your toughest problem. 32+ long
traces at 33MHz. So, I'd consider this. Assume four layers, 1, 2, 3 & 4.
FPGA mounted on layer 1. First, make layer 2 a ground plane. Underneath the
FPGA on layer 1, fill the area with copper and connect to all the Vcco pins.
Layer 3 under the FPGA should be copper flooded for Vccint. You now put a
chunky C shape around the Vccint flood on Layer 3 to route Vccaux.
Via Vccint, Vccaux and Ground to each and every required pin on the FPGA,
but keep the vias inside the square of FPGA pins, to avoid hindering routing
your I/O signals outwards on layer 1. Vcco vias can connect to anywhere on
your layer 1 mini-plane under the FPGA. If you have more than one Vcco, you
can divide up this mini plane, but try to group banks that share a Vcco
together.

On layer 4 under the FPGA, pack with bypass caps for Vcco and Vccint. (Check
XAPP623 for good advice on layout for bypass caps.) You need at least one
via for the power end of the cap, more is better, don't share vias between
caps. Flood the rest of this bit of layer 4 with ground for the bypass caps,
and use many vias to connect this layer 4 ground flood to Layer 2, your
ground plane.

Now, route your signals out on layer 1. Cram them together so that you can
fit extra bypass caps onto layer 1, for each of Vccint, Vcco, Vccaux.
As for bypass caps, use 0805s on layer 4. Use 0402s on layer 1. Via
inductance is around 1.2nH, double the capacitor inductance, so don't worry
about high frequencies on the bottom layer. In fact for a PQ208 the lead
inductance is probably around 10nH, so don't worry about all that 'spread of
capacitance values' crap, big capacitance is beautiful here!

Try it, you never know, you might be one of Austin's lucky ones! ;-)
Cheers, Syms.