Updated Stratix II Power Specs & Explanation

Austin,

You railed against Altera and your comments on the tool and their parts were
obscured by the sheer volume of sarcasm.  Maybe if I knew you, I'd take
extreme sarcasm as appropriate critique; I just wasn't brought up that way.

There are those who believe triple oxide is the way to go.  There are those
who believe low-K dielectric is golden.  There are others in the industry
stepping away from low-K because they see a path to 65 nm and beyond without
the need for the exotic materials.  As with politics and religions, there
are data to back up the claims by both camps, not just "I'm right, you're
stupid."

I find it difficult to ignore "attacks" from any vendor.  I've been
primarily using Xilinx devices over the last decade having first cut my
teeth on the Altera devices.  I prefer brand X because of problems I had
getting appropriate I/O performance on brand A as little as 5 years ago.
For me, brand X was a superior technical solution for my needs.  I don't
like to see anyone "disrespecting my parts" out of spite nor do I like to
see someone in "my camp" producing a virtually useless discourse on how much
the competition lies and cheats.

If someone believes in their product - or religion, or politics - I don't
mind listening to their discourse when it's not offensive.  When their
message degrades to mud slinging and name calling - as it appeared to be
when an Altera marketing VP posted here several months ago - it brings the
whole forum down a notch or two.

It appears Altera's power estimators have some bugs.
It appears Xilinx hasn't published worst-case numbers on all power figures.
It appears Triple Oxide is a win for Xilinx.
It appears Low-K is a win for Altera.
It appears that most marketing messages are more politics and religion than
fact.
It appears Engineers on both sides of the camp believe their marketing.
That's fine.

It appears I get annoyed when people turn argumentative for the sake of
argument.

I've been a hardware engineer at Xerox Corp since '99 - john dot handwork at
office dot xerox dot com - and use my home email to limit spam.  There's
typically no reason for my work email on this forum.  I made Telecomm test
equipment at TTC (Telecommunications Techniques Corp, now Acterna) in
Germantown, Maryland for a dozen years before switching to color laser
printers here in Wilsonville, Oregon.  FPGAs are my daily work.

Thanks for your continued contribution of useful information.  I appreciate
all the folks on this board that help expand my horizons with respect to
FPGA design.  I don't want to be sorry about respecting my field.

- John Handwork


"austin" <austin@xilinx.com> wrote in message
news:curnam$baj2@cliff.xsj.xilinx.com...
> Well,
>
> John, the issue is "what is the leakage current of the new 90nm
> technology node?".
>
> Xilinx has claimed (and we think we have proved it) that the use of
> triple oxide (basically keeping memory cells and pass gates at 130 nm in
> 90nm) gives us both speed, and a 3X leakage advantage.  Not to mention
> an SEU advantage (we haven't even started on that weakness in the
> competition, yet).
>
> They claim that their simpler process is more cost effective (? where
> are the $ quotes ?) and more producable (we are both shipping), and have
> similar or better leakage, and better speed.
>
> These claims are false.  Physics is physics.  No smoke and mirrors 6 lut
> is going to work.
>
> They may have solved the surge issue, but we have yet to see any parts
> where that is true.  It is also true they do not make it easy for Xilinx
> to buy their parts.  We are oblidged to pay for them like any customer,
> so there is a fair and level playing field.   So we admit we may not
> have seen their fixed parts.  Have you?
>
> The engineering community is a group of very well educated professionals
> who deserve to know what is going on.  Most of them have a sense of
> humor, and appreciate the banter, some do not. If you are one who does
> not appreciate my postings, please ignore them.
>
> If you objected to the tone of my posting, I am very sorry:  I can't
> help it when I see such total nonsense being presented (IMHO).
>
> If the gentlemanly thing to do is to respond in a "proper" fashion (in
> your humble opinion), then I will leave that to others, as I am not
> going to live long enough to tolerate such nonsense.  Life is far too
> precious to me to waste.  Perhaps if you knew me better you would
> understand.  Since you do not, please feel free to ignore me.
>
> Again, my intent is to say it like it is, and not to gloss over the fine
> points, as it is the fine points that leave customers' systems broken
> and worthless.
>
> Let me know what you are objecting to specifically:  the truth of the
> matter, or the tone I take.  I can and do apologize, and I am able to
> learn, grow, and change.
>
> austin@xilinx.com
>
> Austin
>
> PS:  from the raw message, I can not see exactly where (or who) you are.
>   I respect that, as I too am inundated with spam, and I understand you
> wishing to avoid that.

<snip>

John,

Thanks for your posting.

A very few comments below.

Austin

John_H wrote:

> Austin,
> 
> You railed against Altera and your comments on the tool and their parts were
> obscured by the sheer volume of sarcasm.  Maybe if I knew you, I'd take
> extreme sarcasm as appropriate critique; I just wasn't brought up that way.

OK, fair enough.  I have been told that my 'style' is a mystery to some. 
  I am working on it.

> 
> There are those who believe triple oxide is the way to go.

We see some benefits:  low leakage for memory and interconnect, higher 
speed for interconnect, better SEU FIT rate (lower) for memory....

   There are those
> who believe low-K dielectric is golden.

We'd love to have lo-K!  But our fabs (yes, plural) could not meet our 
reliability goals for qual.  So we ended up pushing the Vt's to get back 
the speed we lost, and paid for it with slightly increased leakage in V2 
Pro.  In V4, we don't need lo-K to get the speed we needed.

   There are others in the industry
> stepping away from low-K because they see a path to 65 nm and beyond without
> the need for the exotic materials.

As it turns out, we can now have lo-K, and have it committed for 65nm. 
They finally got it working to our requirements.

   As with politics and religions, there
> are data to back up the claims by both camps, not just "I'm right, you're
> stupid."

Well, I would NOT say they are stupid, as they have explained why they 
made their choice:  triple oxide was considered too much of a risk at 
their fab at the time they did their design.  For us, lo-K was 
considered too risky.  You do not get to choose, the fab chooses for you.

> I find it difficult to ignore "attacks" from any vendor.  I've been
> primarily using Xilinx devices over the last decade having first cut my
> teeth on the Altera devices.

Thank you.

   I prefer brand X because of problems I had
> getting appropriate I/O performance on brand A as little as 5 years ago.
> For me, brand X was a superior technical solution for my needs.

I hope we can continue to show that our offering meets your needs.  I am 
sure that Altera can also make a decent showing to meeting your needs, 
as well.

In no way are their parts "bad" or "slow" -- they are a serious 
competitor with a competitive offering (to our Spartan, Virtex 4 LX and 
SX families, although I would state that we have no competition to the 
FX family .... yet).

   I don't
> like to see anyone "disrespecting my parts" out of spite nor do I like to
> see someone in "my camp" producing a virtually useless discourse on how much
> the competition lies and cheats.

Paul does not lie.  He does not cheat.  I did not say that.  If you read 
our postings carefully, you will note that he, and I, are very very 
careful about what we post.

When they ran their benchmarks, they saw a speed improvement.  When we 
run our benchmarks, we see a speed improvement.  When I run our power 
predictor spreadsheet, I see an improvement.  When Paul runs his, he 
sees an improvement.

The devil is in the details: is a static power reduction at 25C an 
improvement?  Yes, and No.  Is comparing our middle speed grade with 
their fastest honest?  Well, if that is the only thing they can get 
their hands on, perhaps it is.  Would it be better to compare their 
slowest with our slowest?  Who would be excited about that?

> 
> If someone believes in their product - or religion, or politics - I don't
> mind listening to their discourse when it's not offensive.  When their
> message degrades to mud slinging and name calling - as it appeared to be
> when an Altera marketing VP posted here several months ago - it brings the
> whole forum down a notch or two.
> 
> It appears Altera's power estimators have some bugs.
> It appears Xilinx hasn't published worst-case numbers on all power figures.

True.  We have not finished all characterization.  Our FAEs have the 
present worst case numbers for customer design, but we prefer to let 
them cool a little longer.  Use Web power to 85 C junction temp and 
multiply by 2.5 to get worst case (for now, until we release the 
finals).  Even then, we are still up to 70% less leakage.

> It appears Triple Oxide is a win for Xilinx.

Yes.  70% better worst case leakage is big.  SEU improvement is good. 
Speed is good.

> It appears Low-K is a win for Altera.

5% less C, means 5% less core power, and ~5% more speed over regular K. 
  All good.

> It appears that most marketing messages are more politics and religion than
> fact.

Sadly, true.

> It appears Engineers on both sides of the camp believe their marketing.

Yup.  But I get to tell marketing what numbers to use, before they use 
them.  I don't know if Paul is also the manager of their 
characterization group.

> That's fine.
> 
> It appears I get annoyed when people turn argumentative for the sake of
> argument.
> 
> I've been a hardware engineer at Xerox Corp since '99 - john dot handwork at
> office dot xerox dot com - and use my home email to limit spam.  There's
> typically no reason for my work email on this forum.  I made Telecomm test
> equipment at TTC (Telecommunications Techniques Corp, now Acterna) in
> Germantown, Maryland for a dozen years before switching to color laser
> printers here in Wilsonville, Oregon.  FPGAs are my daily work.

Cool.  I bought and used TTC test equipment in my 23 years as a 
telecommunications transmissions system designer before I was 
reincarnated as an IC Design Engineer.  Great equipment!

> 
> Thanks for your continued contribution of useful information.  I appreciate
> all the folks on this board that help expand my horizons with respect to
> FPGA design.

You are welcome.

   I don't want (you) to be sorry about respecting my field.
> 
> - John Handwork
> 
> 
> "austin" <austin@xilinx.com> wrote in message
> news:curnam$baj2@cliff.xsj.xilinx.com...
> 
>>Well,
>>
>>John, the issue is "what is the leakage current of the new 90nm
>>technology node?".
>>
>>Xilinx has claimed (and we think we have proved it) that the use of
>>triple oxide (basically keeping memory cells and pass gates at 130 nm in
>>90nm) gives us both speed, and a 3X leakage advantage.  Not to mention
>>an SEU advantage (we haven't even started on that weakness in the
>>competition, yet).
>>
>>They claim that their simpler process is more cost effective (? where
>>are the $ quotes ?) and more producable (we are both shipping), and have
>>similar or better leakage, and better speed.
>>
>>These claims are false.  Physics is physics.  No smoke and mirrors 6 lut
>>is going to work.
>>
>>They may have solved the surge issue, but we have yet to see any parts
>>where that is true.  It is also true they do not make it easy for Xilinx
>>to buy their parts.  We are oblidged to pay for them like any customer,
>>so there is a fair and level playing field.   So we admit we may not
>>have seen their fixed parts.  Have you?
>>
>>The engineering community is a group of very well educated professionals
>>who deserve to know what is going on.  Most of them have a sense of
>>humor, and appreciate the banter, some do not. If you are one who does
>>not appreciate my postings, please ignore them.
>>
>>If you objected to the tone of my posting, I am very sorry:  I can't
>>help it when I see such total nonsense being presented (IMHO).
>>
>>If the gentlemanly thing to do is to respond in a "proper" fashion (in
>>your humble opinion), then I will leave that to others, as I am not
>>going to live long enough to tolerate such nonsense.  Life is far too
>>precious to me to waste.  Perhaps if you knew me better you would
>>understand.  Since you do not, please feel free to ignore me.
>>
>>Again, my intent is to say it like it is, and not to gloss over the fine
>>points, as it is the fine points that leave customers' systems broken
>>and worthless.
>>
>>Let me know what you are objecting to specifically:  the truth of the
>>matter, or the tone I take.  I can and do apologize, and I am able to
>>learn, grow, and change.
>>
>>austin@xilinx.com
>>
>>Austin
>>
>>PS:  from the raw message, I can not see exactly where (or who) you are.
>>  I respect that, as I too am inundated with spam, and I understand you
>>wishing to avoid that.
> 
> 
> <snip>
> 
> 

Austin Lesea wrote:
(big snip)

> The devil is in the details: is a static power reduction at 25C an 
> improvement?  Yes, and No.  Is comparing our middle speed grade with 
> their fastest honest?  Well, if that is the only thing they can get 
> their hands on, perhaps it is.  Would it be better to compare their 
> slowest with our slowest?  Who would be excited about that?

I wonder what fraction of FPGA designs are not very speed 
sensitive.  I used to wonder about that in TTL days, building
digital clocks (60Hz for the fastest signals) out of 30MHz TTL 
chips.

Many designs could easily only require on half or one tenth of 
what current FPGAs are capable of, and still be worth putting in 
an FPGA.  For those, the slowest devices, especially with lower 
static power, might be very useful.

For the most part, I don't find this discussion very useful.
We all know about marketing departments, and having engineers
argue this doesn't cause me to look favorable on their company 
or products.

-- glen

glen herrmannsfeldt wrote:
> Austin Lesea wrote:
> (big snip)
>
> > The devil is in the details: is a static power reduction at 25C an
> > improvement?  Yes, and No.  Is comparing our middle speed grade
with
> > their fastest honest?  Well, if that is the only thing they can get

> > their hands on, perhaps it is.  Would it be better to compare their

> > slowest with our slowest?  Who would be excited about that?
>
> I wonder what fraction of FPGA designs are not very speed
> sensitive.  I used to wonder about that in TTL days, building
> digital clocks (60Hz for the fastest signals) out of 30MHz TTL
> chips.
>
> Many designs could easily only require on half or one tenth of
> what current FPGAs are capable of, and still be worth putting in
> an FPGA.  For those, the slowest devices, especially with lower
> static power, might be very useful.
>
> For the most part, I don't find this discussion very useful.
> We all know about marketing departments, and having engineers
> argue this doesn't cause me to look favorable on their company
> or products.
> 
> -- glen

> Well, I would NOT say they are stupid, as they have explained why
they
> made their choice:  triple oxide was considered too much of a risk at

> their fab at the time they did their design.  For us, lo-K was
> considered too risky.  You do not get to choose, the fab chooses for
you.

No, the main reason we chose not to use triple oxide was we found that
it hurts speed too much for the resulting reduction in static power.
There are other levers to use (varying gate length, threshold voltage)
that also reduce static power and can do so with less speed hit.
Obviously, your engineers came to a different conclusion.

My guess is the real reason for the difference in approach comes down
to different product goals and performance/power targets.  In the end,
we chose a different point on the speed vs. static power curve for
Stratix II than you did for V4.  You can talk about "system
performance" until you are blue in the face, but in the end our logic +
routing fabric is significantly faster than V4s.  That's where the bulk
of the transistors are still, and we chose faster, leakier transistors
where you chose slow, less leaky ones.

Regards,

Paul Leventis
Altera Corp.

> True.  We have not finished all characterization.  Our FAEs have the
> present worst case numbers for customer design, but we prefer to let
> them cool a little longer.  Use Web power to 85 C junction temp and
> multiply by 2.5 to get worst case (for now, until we release the
> finals).  Even then, we are still up to 70% less leakage.

Could you post some details on how you are getting this "up to" 70%
leakage number?

If I take 85C Typical data from WPT4.0 for V4 and multply by 2.5
(VccInt + VccAux), and compare to 85C Maximum data from the PowerPlay
Early Power Estimator 2.1 for Stratix II (VccInt + VccPD), here is what
I find.

   LX15     580 mW   2S15   825 mW     -29%
   LX25     840 mW
   LX40    1212 mW   2S30  1191 mW     +2%
   LX60    1782 mW   2S60  2232 mW     -20%
   LX80    2210 mW
   LX100   2817 mW   2S90  3233 mW     -13%
   LX160   3727 mW   2S130 4411 mW     -15%
   LX200   4542 mW   2S180 5445 mW     -17%

I have a graph that plots vs. normalized LE count since device sizes
don't line up perfectly, but you get the picture.

Now I know the 2.5x factor is a rough estimate on your part, but I
still find it hard to see a massive V4 advantage on static power here.
And if we add in our dynamic power advantage (see Vaughn's posting)...

Regards,

Paul Leventis
Altera Corp.

Paul,

OK.  There it is folks:  they are leakier.  Seems their fab did not show 
any improvements they felt were worth having.

And, if you decide to use only LUTs and interconnect, and not take 
advantage of any advanced features (SRL, LUT RAM, FIFO/BRAM, BRAM w/ECC, 
PPC, EMAC, DSP48, and so on and so forth), nor attempt to push our 
tools, you can also get faster performance, too. (Although I am still 
very suspicious of this claim).

But, if you are serious about static power, and concerned about getting 
the best performance, and willing to actually use some of the hardened 
(faster) functions, then I ask you to consider the Virtex 4 FPGA.

And if you need built in source synchronous IO with individual pin 
settable or adjustable delays, 450 MHz PPC, EMACs, or MGTs, well, there 
is no other choice, is there?

Austin

Paul Leventis wrote:

>>Well, I would NOT say they are stupid, as they have explained why
> 
> they
> 
>>made their choice:  triple oxide was considered too much of a risk at
> 
> 
>>their fab at the time they did their design.  For us, lo-K was
>>considered too risky.  You do not get to choose, the fab chooses for
> 
> you.
> 
> No, the main reason we chose not to use triple oxide was we found that
> it hurts speed too much for the resulting reduction in static power.
> There are other levers to use (varying gate length, threshold voltage)
> that also reduce static power and can do so with less speed hit.
> Obviously, your engineers came to a different conclusion.
> 
> My guess is the real reason for the difference in approach comes down
> to different product goals and performance/power targets.  In the end,
> we chose a different point on the speed vs. static power curve for
> Stratix II than you did for V4.  You can talk about "system
> performance" until you are blue in the face, but in the end our logic +
> routing fabric is significantly faster than V4s.  That's where the bulk
> of the transistors are still, and we chose faster, leakier transistors
> where you chose slow, less leaky ones.
> 
> Regards,
> 
> Paul Leventis
> Altera Corp.
> 

Paul,

Sign up, and watch Peter.

Austin

Paul Leventis wrote:

>>True.  We have not finished all characterization.  Our FAEs have the
>>present worst case numbers for customer design, but we prefer to let
>>them cool a little longer.  Use Web power to 85 C junction temp and
>>multiply by 2.5 to get worst case (for now, until we release the
>>finals).  Even then, we are still up to 70% less leakage.
> 
> 
> Could you post some details on how you are getting this "up to" 70%
> leakage number?
> 
> If I take 85C Typical data from WPT4.0 for V4 and multply by 2.5
> (VccInt + VccAux), and compare to 85C Maximum data from the PowerPlay
> Early Power Estimator 2.1 for Stratix II (VccInt + VccPD), here is what
> I find.
> 
>    LX15     580 mW   2S15   825 mW     -29%
>    LX25     840 mW
>    LX40    1212 mW   2S30  1191 mW     +2%
>    LX60    1782 mW   2S60  2232 mW     -20%
>    LX80    2210 mW
>    LX100   2817 mW   2S90  3233 mW     -13%
>    LX160   3727 mW   2S130 4411 mW     -15%
>    LX200   4542 mW   2S180 5445 mW     -17%
> 
> I have a graph that plots vs. normalized LE count since device sizes
> don't line up perfectly, but you get the picture.
> 
> Now I know the 2.5x factor is a rough estimate on your part, but I
> still find it hard to see a massive V4 advantage on static power here.
> And if we add in our dynamic power advantage (see Vaughn's posting)...
> 
> Regards,
> 
> Paul Leventis
> Altera Corp.
> 

I did.  My question remains unanswered.

- Paul

Thanks to John for a thoughtful posting.  I enjoy reading this newsgroup and 
helping customers when I can. I also can't resist correcting errors / 
misrepresentations when I see them.  I don't think name calling or hyperbole 
is enjoyable for either the people posting or the people reading posts, so I 
appreciate the effort to encourage civility.

Hopefully correcting the error below will not cause a firestorm in response:

>> It appears Low-K is a win for Altera.
>
> 5% less C, means 5% less core power, and ~5% more speed over regular K. 
> All good.

FSG dielectric (Virtex4) has a dielectric constant of 3.7.  Black diamond 
(Stratix II) has a dielectric constant of about 3.0.  See 
http://www.micromagazine.com/archive/04/03/applied.html for details on the 
dielectric constant of black diamond.  That means you get a 19% capacitance 
reduction with black diamond vs. FSG.  Everybody remembers capacitance is 
directly proportional to dielectric constant, right? :).

So all metal capacitance drops by 19%.  Nowadays metal capacitance is about 
2/3 of the switching capacitance in an FPGA, while the remaining 1/3 is gate 
& diffusion capacitance that is unaffected by low-k (since it's transistor 
capacitance rather than in the metal stack).  So,  you get an ~13% speed up 
and ~13% dynamic power reduction from the use of a low-k dielectric.

Vaughn Betz
Altera
[v b e t z (at) altera.com]