FPGA Market Entry Barriers

On Thursday, October 18, 2018 at 10:53:31 PM UTC-4, Kevin Neilson wrote:
> On Thursday, October 18, 2018 at 9:22:47 AM UTC-6, gnuarm.del...@gmail.com wrote:
> > I was wondering what the barriers are to new companies marketing FPGAs.  Some of the technological barriers are obvious.  Designing a novel device is not so easy as the terrain is widely explored, so I expect any new player would need to find a niche application of an unexplored technological feature.  
> > 
> > Silicon Blue exploited a low power technology optimized for low cost devices in mobile applications.  They were successful enough to be bought by Lattice and are still in production with the product line expanded considerably.  
> > 
> > I believe Achronix started out with the idea of asynchronous logic.  I'm not clear if they continue to use that or not, but it is not apparent from their web site.  Their target is ultra fast clock speeds enabling FPGAs in new market.  I don't see then showing up on FPGA vendor lists so I assume they are sill pretty low volume. 
> > 
> > Tabula was based on 3D technology, but they don't appear to have lasted.  I believe they were also claiming an ability to reconfigure logic in real time which sounds like a very complex technology to master.  Not sure what market they were targeting. 
> > 
> > Other than the technologies, what other barriers do new FPGA companies face? 
> > 
> > Rick C.
> 
> I put a little more thought into this:  what if I wanted to start an FPGA company?  I could try to find an innovation or new niche, but that usually fails, partly because people don't want to migrate to something new.  I sure don't.
> 
> Say I want to make regular FPGA.  First I have to make the silicon, which is hard, but let's assume I use a regular architecture with 6-input LUTs and maybe some block RAMs and DSP multipliers.  No processor cores or anything.  I wouldn't want to try to make my own simulator.  I know FPGA companies try to make their own so customers can get a cheap version but I'd try to avoid that.  I'd also farm out the synthesis as much as possible.  I'd get Synplify to do that.  I still have to make the place & route tool and timing analysis tools unless I can find somebody who is already doing that and can just have them adopt my architecture.
> 
> So now I have a pretty standard FPGA, and maybe some tools, but I still have to compete with the established duopoly and their marketing and distribution networks.  Could I compete on price?  I doubt it.  I'm not sure anybody has a compelling reason to switch to me.

Yes, with the approach you describe, being the new, mediocre FPGA company, success is anything but assured.  

I think the given is that there has to be something different about your devices or at least your approach.  I donn't know if the Silicon Blue devices are as much different technologically or if they simply used conventional features with a different focus.  I do know that when Lattice took them over they bent the - still in final development - iCE40 devices back toward the mainstream with higher speeds and losing a bit on the low static power.  Not a big change, but interesting none the less. 

Rick C.

On 18/10/2018 19:41, Kevin Neilson wrote:
> On Thursday, October 18, 2018 at 9:22:47 AM UTC-6, gnuarm.del...@gmail.com wrote:
..snip
>>
>> Rick C.
> 
> I've always wondered.  So many companies have entered and then departed, leaving the duopoly.  I think it must be the problem of developing the tools.  As poor as they are, I think that might be the biggest impediment.  Every grand new idea seems to flounder in the face of what works.  Most innovations from Xilinx itself seem to flounder.  Does anybody really use partial reconfiguration, years and years after it was introduced?  

Yes of course, why do you think companies like Xilinx spend so much 
money on developing it? Is it to make sure their developers are not 
getting bored, they have money to burn or is it simply because their 
high-end customers (clearly not you) require it?
If you work on a complex bit of IP which required physical synthesis, 
hand placement etc to meet timing wouldn't you want a way to preserve 
it? Do you think companies will simply re-synthesize, P&R and 
re-validate the whole design (or IP block) again after making a small 
change?

All the "high-level" synthesis tools are either defunct or should be 
defunct.

Why should be defunct? Playing with Flipflops, shift registers, luts etc 
is nothing more than assembly for programmable logic. There is nothing 
more painful to discovered that your carefully hand-crafted RTL design 
which you spend many man-years of effort on requires and extra pipeline 
stage or you need to reduce resources as you are over resourced. 
Wouldn't it be nice if you could write your design in sequential untimed 
code and use a tool to generate the architecture for you based on 
resource and timing constraints? There are some very successful HLS 
tools (CatapultC, Stratus, Synphony) but given their price they are 
mainly used by high-end companies (the so called 20%). Xilinx's Vivado 
HLS is the exception as it is quite affordable but from what I 
understand not as capable as the others. Yes I know it still requires 
tweaking and FPGA/ASIC know-how but these tools are in full production 
for many years and are used successfully by many companies. More and 
more EDA supplier are starting to offer these tools, they can't be all 
wrong, right?

Hans.
www.ht-lab.com

> Wouldn't it be nice if you could write your design in sequential untimed 
> code and use a tool to generate the architecture for you based on 
> resource and timing constraints? 

Well, yes, it would be nice if such a tool existed.  It doesn't.  If it did, people wouldn't be paying me to make hand-pipelined designs.  People wouldn't pay me to spend two months doing what I can model in Matlab in two lines of code.

On Thursday, October 18, 2018 at 9:48:47 PM UTC-6, gnuarm.del...@gmail.com wrote:
> On Thursday, October 18, 2018 at 10:53:31 PM UTC-4, Kevin Neilson wrote:
> > On Thursday, October 18, 2018 at 9:22:47 AM UTC-6, gnuarm.del...@gmail.com wrote:
> > > I was wondering what the barriers are to new companies marketing FPGAs.  Some of the technological barriers are obvious.  Designing a novel device is not so easy as the terrain is widely explored, so I expect any new player would need to find a niche application of an unexplored technological feature.  
> > > 
> > > Silicon Blue exploited a low power technology optimized for low cost devices in mobile applications.  They were successful enough to be bought by Lattice and are still in production with the product line expanded considerably.  
> > > 
> > > I believe Achronix started out with the idea of asynchronous logic.  I'm not clear if they continue to use that or not, but it is not apparent from their web site.  Their target is ultra fast clock speeds enabling FPGAs in new market.  I don't see then showing up on FPGA vendor lists so I assume they are sill pretty low volume. 
> > > 
> > > Tabula was based on 3D technology, but they don't appear to have lasted.  I believe they were also claiming an ability to reconfigure logic in real time which sounds like a very complex technology to master.  Not sure what market they were targeting. 
> > > 
> > > Other than the technologies, what other barriers do new FPGA companies face? 
> > > 
> > > Rick C.
> > 
> > I put a little more thought into this:  what if I wanted to start an FPGA company?  I could try to find an innovation or new niche, but that usually fails, partly because people don't want to migrate to something new.  I sure don't.
> > 
> > Say I want to make regular FPGA.  First I have to make the silicon, which is hard, but let's assume I use a regular architecture with 6-input LUTs and maybe some block RAMs and DSP multipliers.  No processor cores or anything.  I wouldn't want to try to make my own simulator.  I know FPGA companies try to make their own so customers can get a cheap version but I'd try to avoid that.  I'd also farm out the synthesis as much as possible.  I'd get Synplify to do that.  I still have to make the place & route tool and timing analysis tools unless I can find somebody who is already doing that and can just have them adopt my architecture.
> > 
> > So now I have a pretty standard FPGA, and maybe some tools, but I still have to compete with the established duopoly and their marketing and distribution networks.  Could I compete on price?  I doubt it.  I'm not sure anybody has a compelling reason to switch to me.
> 
> Yes, with the approach you describe, being the new, mediocre FPGA company, success is anything but assured.  
> 
> I think the given is that there has to be something different about your devices or at least your approach.  I donn't know if the Silicon Blue devices are as much different technologically or if they simply used conventional features with a different focus.  I do know that when Lattice took them over they bent the - still in final development - iCE40 devices back toward the mainstream with higher speeds and losing a bit on the low static power.  Not a big change, but interesting none the less. 
> 
> Rick C.

For some satellite work I used the Microsemi RTAX, which filled a niche for rad-hard designs.  It was slow, had few gates, could only be burned once, and had poor tools, but still had a small market.  They made up for low volume with high prices.  I think they're still around.  Since I work with a lot of Galois arithmetic, one thing I'd like to see is an FPGA with special structures for Galois matrix multipliers (instead of, say, DSP48s) and matrix transposers, but I don't think the demand is enough to warrant a special architecture.

On 10/19/18 12:39 PM, Kevin Neilson wrote:
> For some satellite work I used the Microsemi RTAX, which filled a niche for rad-hard designs.  It was slow, had few gates, could only be burned once, and had poor tools, but still had a small market.  They made up for low volume with high prices.  I think they're still around.  Since I work with a lot of Galois arithmetic, one thing I'd like to see is an FPGA with special structures for Galois matrix multipliers (instead of, say, DSP48s) and matrix transposers, but I don't think the demand is enough to warrant a special architecture.

Microsemi is still around (though part of Microchip now). They have a
number of FPGA families, that are somewhat distinct from the big two.

On Saturday, October 20, 2018 at 12:28:51 PM UTC-4, Richard Damon wrote:
> On 10/19/18 12:39 PM, Kevin Neilson wrote:
> > For some satellite work I used the Microsemi RTAX, which filled a niche for rad-hard designs.  It was slow, had few gates, could only be burned once, and had poor tools, but still had a small market.  They made up for low volume with high prices.  I think they're still around.  Since I work with a lot of Galois arithmetic, one thing I'd like to see is an FPGA with special structures for Galois matrix multipliers (instead of, say, DSP48s) and matrix transposers, but I don't think the demand is enough to warrant a special architecture.
> 
> Microsemi is still around (though part of Microchip now). They have a
> number of FPGA families, that are somewhat distinct from the big two.

I've never found the Actel devices to be a good solution for any of my problems.  Mostly they follow the same path that the big two follow regarding packages, namely larger, more pins and more dollars that optimal for my designs.  I find Lattice is the only company that has much in the smaller packages with a low enough price.  

I wonder what Microchip will do with the FPGA product line now.  I see they have Atmel's CPLD/SPLD line as well as the rather obsolete AT40K products, but nothing of the Actel devices.  I guess they are presently running Microsemi as a separate company for now. 

Rick C.

gnuarm.deletethisbit@gmail.com writes:

> I believe Achronix started out with the idea of asynchronous logic.
> I'm not clear if they continue to use that or not, but it is not
> apparent from their web site.  Their target is ultra fast clock speeds
> enabling FPGAs in new market.  I don't see then showing up on FPGA
> vendor lists so I assume they are sill pretty low volume.

I think Achronix is embedded FPGAs only at this point.

> Tabula was based on 3D technology, but they don't appear to have
> lasted.  I believe they were also claiming an ability to reconfigure
> logic in real time which sounds like a very complex technology to
> master.  Not sure what market they were targeting.

I spoke with an ex-Achronix guy a few years ago in a conference. He was
confident that Tabula never had their mystical reconfiguring tech
working and that the whole company was a scam. He basically said they
are good with muxes and suck with random logic. Tabula was at the
conference demonstrating some kind of ethernet switch which would be
mostly muxes... No idea if he was right or wrong. He was expecting
Achronix to go under too. Tabula closed in 2015 and apparently Altera
hired some of the team and maybe some of Tabula's IP. But I don't see
them putting out anything resembling what Tabula claimed to have.

> Other than the technologies, what other barriers do new FPGA companies face? 

Really the question is, how much better than Xilinx or Intel would you
need to be to break into the market? You'd probably need a billionaire
who'd want to disrupt the market. Musk and Tesla come to mind. Other
possibility I can think of is state funded efforts from China, I think I
read they've increased funding for hardware research considerably.

I remember an interview with a Flex Logix founder, they do embedded
FPGAs only. He basically said he had no interest in trying to compete
with the two giants and so he found a niche. The niche may have grown,
Achronix is there too and I think I heard old timer QuickLogic also
plays in that business now. Probably some other startups too.

Come to think of it, it would be interesting to know what companies and
what chips actually integrate FPGAs and do they farm out the design
work?  Or is it the embedded FPGA provider who does the design work for
the programmable part?

On Tuesday, October 23, 2018 at 6:50:48 AM UTC-4, Anssi Saari wrote:
> gnuarm.deletethisbit@gmail.com writes:
> 
> > I believe Achronix started out with the idea of asynchronous logic.
> > I'm not clear if they continue to use that or not, but it is not
> > apparent from their web site.  Their target is ultra fast clock speeds
> > enabling FPGAs in new market.  I don't see then showing up on FPGA
> > vendor lists so I assume they are sill pretty low volume.
> 
> I think Achronix is embedded FPGAs only at this point.
> 
> > Tabula was based on 3D technology, but they don't appear to have
> > lasted.  I believe they were also claiming an ability to reconfigure
> > logic in real time which sounds like a very complex technology to
> > master.  Not sure what market they were targeting.
> 
> I spoke with an ex-Achronix guy a few years ago in a conference. He was
> confident that Tabula never had their mystical reconfiguring tech
> working and that the whole company was a scam. He basically said they
> are good with muxes and suck with random logic. Tabula was at the
> conference demonstrating some kind of ethernet switch which would be
> mostly muxes... No idea if he was right or wrong. He was expecting
> Achronix to go under too. Tabula closed in 2015 and apparently Altera
> hired some of the team and maybe some of Tabula's IP. But I don't see
> them putting out anything resembling what Tabula claimed to have.
> 
> > Other than the technologies, what other barriers do new FPGA companies face? 
> 
> Really the question is, how much better than Xilinx or Intel would you
> need to be to break into the market? You'd probably need a billionaire
> who'd want to disrupt the market. Musk and Tesla come to mind. Other
> possibility I can think of is state funded efforts from China, I think I
> read they've increased funding for hardware research considerably.
> 
> I remember an interview with a Flex Logix founder, they do embedded
> FPGAs only. He basically said he had no interest in trying to compete
> with the two giants and so he found a niche. The niche may have grown,
> Achronix is there too and I think I heard old timer QuickLogic also
> plays in that business now. Probably some other startups too.

Yes, I guess embedded PIP (Programmable Intellectual Property) is a niche.  I think there are other niches.  Lattice found (or bought a company who found) a niche for low power, small FPGAs.  I expect there are others.  Or you can market devices differently.  I suppose X and A know where their bread is buttered, but I have always felt that FPGAs were underexploited and could very easily be used like MCUs if they were marketed like MCUs.  Lots of flavors in lots of packages.  Xilinx has always acted like it can't afford to produce a wider range of packages.  10,000 LUTs is still a small chip.  Give it as many I/Os as a 48 pin QFP will support and I think it will be able to do a lot more than MCUs.  Some people think the propeller is great, but you could have 30, 40 or even 50 small soft-cores in a small FPGA all working independently.  


> Come to think of it, it would be interesting to know what companies and
> what chips actually integrate FPGAs and do they farm out the design
> work?  Or is it the embedded FPGA provider who does the design work for
> the programmable part?

Having all the work done by the FPGA provider would limit the number of applications.  

Rick C.

On 19/10/2018 17:14, Kevin Neilson wrote:
>> Wouldn't it be nice if you could write your design in sequential untimed
>> code and use a tool to generate the architecture for you based on
>> resource and timing constraints?
> 
> Well, yes, it would be nice if such a tool existed.  It doesn't.  

It does. If you ever visit DVCon, DAC, DATE etc go to the 
Mentor/Synopsys/Cadence/Xilinx stand and tell them you are interested in 
architectural exploration using untimed C/C++ code.

If it did, people wouldn't be paying me to make hand-pipelined designs.

What about a) your clients are not willing to change their design to 
untimed C/C++ code? b) it is cheaper to pay a contractor for 2 month 
than it is to pay $100K+ for an HLS tool?

People wouldn't pay me to spend two months doing what I can model in 
Matlab in two lines of code.
>
I do hope you are not working for Xilinx as they will call you in for a 
mandatory training session on Vivado's HLS :-)

https://www.xilinx.com/video/hardware/vivado-hls-in-depth-technical-overview.html

After watching this consider what a top of the range HLS tool can do.

Hans
www.ht-lab.com

Niches have to be large enough to allow the costs of the masks and engineering to be recovered.

The use of open source tools let the ICE40 be used in applications such as Raspberry Pi "hats", but the 8Kluts limit is restricting this niche.

Some hobbyists long for DIP packages and 5V i/o. Though this is a tiny niche, using an obsolete node (like 250nm or 350nm) might make crowdfunding practical. It would probably be more popular than 

https://www.crowdsupply.com/chips4makers/retro-uc

About SiliconBlue, part of their motivation were the expiration of a bunch of FPGA patents. Even more have expired since then.

-- Jecel