Need help to understand: Efficient Multi-Ported Memories for FPGAs

Hi,

I cannot understand the following paper:
"Efficient Multi-Ported Memories for FPGAs" 

http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf

FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read.

The paper essence for 2 write ports and 2 read ports is:
There are 2 memory blocks each having 1 write port and 2 read ports.

The 2 memory blocks provide 2 write ports to write independently.

There is another memory block, called LVT (Live Value Table), with 2 write ports and 2 read ports, each cell of which stores the port number which holds the latest write data.

Example:

simultaneously:
Write through port 1 with address 3; --- no problem

Write through port 0 with address 2;

simultaneously:
0 --> LVT(2); 
1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?

If above 2 simultaneously write operation are feasible, 2 read operations can read from LVT first to get proper port number, and then get the correct latest data read from the port number.

Thank you.

Weng 

On 14/01/2019 19:54, Weng Tianxiang wrote:
> Hi,
> 
> I cannot understand the following paper:
> "Efficient Multi-Ported Memories for FPGAs"
> 
> http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
> 
> FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read.
> 
> The paper essence for 2 write ports and 2 read ports is:
> There are 2 memory blocks each having 1 write port and 2 read ports.
> 
> The 2 memory blocks provide 2 write ports to write independently.
> 
> There is another memory block, called LVT (Live Value Table), with 2 write ports and 2 read ports, each cell of which stores the port number which holds the latest write data.
> 
> Example:
> 
> simultaneously:
> Write through port 1 with address 3; --- no problem
> 
> Write through port 0 with address 2;
> 
> simultaneously:
> 0 --> LVT(2);
> 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
> 
> If above 2 simultaneously write operation are feasible, 2 read operations can read from LVT first to get proper port number, and then get the correct latest data read from the port number.
> 
> Thank you.
> 
> Weng
> 

Hi Weng,

It is quite a simple scheme, assume you have 2 write ports each writing 
into their own blockram. If port0 write to address 0x12 and port1 writes 
to address 0x15 then the LVT (single bit array in this case) will store 
array[12]=0 and array[15]=1.
Then if a read port read from address 15 the LVT array will set the mux 
to 1 which connect the second blockram to the output.

I use the XOR variant in my processor for a 8w8r block.

Good luck,
Hans
www.ht-lab.com

On Monday, January 14, 2019 at 1:23:01 PM UTC-8, HT-Lab wrote:
> On 14/01/2019 19:54, Weng Tianxiang wrote:
> > Hi,
> > 
> > I cannot understand the following paper:
> > "Efficient Multi-Ported Memories for FPGAs"
> > 
> > http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
> > 
> > FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read.
> > 
> > The paper essence for 2 write ports and 2 read ports is:
> > There are 2 memory blocks each having 1 write port and 2 read ports.
> > 
> > The 2 memory blocks provide 2 write ports to write independently.
> > 
> > There is another memory block, called LVT (Live Value Table), with 2 write ports and 2 read ports, each cell of which stores the port number which holds the latest write data.
> > 
> > Example:
> > 
> > simultaneously:
> > Write through port 1 with address 3; --- no problem
> > 
> > Write through port 0 with address 2;
> > 
> > simultaneously:
> > 0 --> LVT(2);
> > 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
> > 
> > If above 2 simultaneously write operation are feasible, 2 read operations can read from LVT first to get proper port number, and then get the correct latest data read from the port number.
> > 
> > Thank you.
> > 
> > Weng
> > 
> 
> Hi Weng,
> 
> It is quite a simple scheme, assume you have 2 write ports each writing 
> into their own blockram. If port0 write to address 0x12 and port1 writes 
> to address 0x15 then the LVT (single bit array in this case) will store 
> array[12]=0 and array[15]=1.
> Then if a read port read from address 15 the LVT array will set the mux 
> to 1 which connect the second blockram to the output.
> 
> I use the XOR variant in my processor for a 8w8r block.
> 
> Good luck,
> Hans
> www.ht-lab.com

Hi Hans,

"If port0 write to address 0x12 and port1 writes 
to address 0x15 then the LVT (single bit array in this case) will store 
array[12]=0 and array[15]=1. "

How do you do: 0 --> array[12], 1 --> array[15] on the same cycle?

Thank you.

Weng

On Monday, January 14, 2019 at 4:23:01 PM UTC-5, HT-Lab wrote:
> On 14/01/2019 19:54, Weng Tianxiang wrote:
> > Hi,
> > 
> > I cannot understand the following paper:
> > "Efficient Multi-Ported Memories for FPGAs"
> > 
> > http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
> > 
> > FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read.
> > 
> > The paper essence for 2 write ports and 2 read ports is:
> > There are 2 memory blocks each having 1 write port and 2 read ports.
> > 
> > The 2 memory blocks provide 2 write ports to write independently.
> > 
> > There is another memory block, called LVT (Live Value Table), with 2 write ports and 2 read ports, each cell of which stores the port number which holds the latest write data.
> > 
> > Example:
> > 
> > simultaneously:
> > Write through port 1 with address 3; --- no problem
> > 
> > Write through port 0 with address 2;
> > 
> > simultaneously:
> > 0 --> LVT(2);
> > 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
> > 
> > If above 2 simultaneously write operation are feasible, 2 read operations can read from LVT first to get proper port number, and then get the correct latest data read from the port number.
> > 
> > Thank you.
> > 
> > Weng
> > 
> 
> Hi Weng,
> 
> It is quite a simple scheme, assume you have 2 write ports each writing 
> into their own blockram. If port0 write to address 0x12 and port1 writes 
> to address 0x15 then the LVT (single bit array in this case) will store 
> array[12]=0 and array[15]=1.
> Then if a read port read from address 15 the LVT array will set the mux 
> to 1 which connect the second blockram to the output.
> 
> I use the XOR variant in my processor for a 8w8r block.

Our patent seeking friend fails to understand the very basic issue of how a multi-write port RAM can operate.  The paper describes how you can fake a multi-write port RAM using multiple single-write port RAMs using a smaller word size multi-write port RAM.  This smaller RAM can be constructed from logic in the FPGA fabric which is clearly explained in the paper. 

Sometimes you need to actually understand the field you are trying to seek patents in.  Or you can just use a shotgun approach and obtain many patents hoping someday one of them ends up paying off.  

  Rick C.

  - Get 6 months of free supercharging
  - Tesla referral code - https://ts.la/richard11209

On 1/14/19 1:22 PM, HT-Lab wrote:
> On 14/01/2019 19:54, Weng Tianxiang wrote:
>> Hi,
>>
>> I cannot understand the following paper:
>> "Efficient Multi-Ported Memories for FPGAs"
>>
>> http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
>>
>> FPGA has a structure with 1 write port and 2 read port memory block: 2 
>> memory blocks sharing the same write port and each of 2 blocks can be 
>> read individually by 2 different read.
>>
>> The paper essence for 2 write ports and 2 read ports is:
>> There are 2 memory blocks each having 1 write port and 2 read ports.
>>
>> The 2 memory blocks provide 2 write ports to write independently.
>>
>> There is another memory block, called LVT (Live Value Table), with 2 
>> write ports and 2 read ports, each cell of which stores the port 
>> number which holds the latest write data.
>>
>> Example:
>>
>> simultaneously:
>> Write through port 1 with address 3; --- no problem
>>
>> Write through port 0 with address 2;
>>
>> simultaneously:
>> 0 --> LVT(2);
>> 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
>>
>> If above 2 simultaneously write operation are feasible, 2 read 
>> operations can read from LVT first to get proper port number, and then 
>> get the correct latest data read from the port number.
>>
>> Thank you.
>>
>> Weng
>>
> 
> Hi Weng,
> 
> It is quite a simple scheme, assume you have 2 write ports each writing 
> into their own blockram. If port0 write to address 0x12 and port1 writes 
> to address 0x15 then the LVT (single bit array in this case) will store 
> array[12]=0 and array[15]=1.
> Then if a read port read from address 15 the LVT array will set the mux 
> to 1 which connect the second blockram to the output.
> 
> I use the XOR variant in my processor for a 8w8r block.
> 
> Good luck,
> Hans
> www.ht-lab.com
> 

Although the kicker with this paper is in simultaneous reads.  They 
gloss pretty hard over the fact that (per the end of 5.3 and 5.4), for N 
write ports and M read ports, you need N*M redundant BRAMs.  For their 
example of a 4-write, 8-read RAM they're using 32-fold the actual RAM 
requirements.  Can't even take advantage of BRAM packing, since they use 
both ports of each RAM to keep one dedicated write port and one 
dedicated read.  32x is a hell of a multiplier to be fighting against; 
it'll chew up all the RAM in a cheap FPGA before you can bat an eye.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

On Monday, January 14, 2019 at 6:15:17 PM UTC-5, Rick C. Hodgin wrote:
> On Monday, January 14, 2019 at 5:42:37 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > Our patent seeking friend fails to understand the very basic issue
> > of how a multi-write port RAM can operate.
> 
> Always there with a pure heart of kindness, one given to teaching,
> apt to help compensate when someone is perhaps less than they should
> be.  Always accommodating, always uplifting, always at the ready to
> improve another's life, eh Rick?

I am happy to answer questions and provide advice to those who ask for it.  Sometimes the person finds it useful other times not.  I am not alone in offering the same sort of help to more than one person in this group.  But it is often declined presumably because the person asking for help doesn't really want help as much as getting others to do their work for them.  

  Rick C.

  + Get 6 months of free supercharging
  + Tesla referral code - https://ts.la/richard11209

On Monday, January 14, 2019 at 6:38:35 PM UTC-5, Rob Gaddi wrote:
> On 1/14/19 1:22 PM, HT-Lab wrote:
> > On 14/01/2019 19:54, Weng Tianxiang wrote:
> >> Hi,
> >>
> >> I cannot understand the following paper:
> >> "Efficient Multi-Ported Memories for FPGAs"
> >>
> >> http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
> >>
> >> FPGA has a structure with 1 write port and 2 read port memory block: 2=
=20
> >> memory blocks sharing the same write port and each of 2 blocks can be=
=20
> >> read individually by 2 different read.
> >>
> >> The paper essence for 2 write ports and 2 read ports is:
> >> There are 2 memory blocks each having 1 write port and 2 read ports.
> >>
> >> The 2 memory blocks provide 2 write ports to write independently.
> >>
> >> There is another memory block, called LVT (Live Value Table), with 2=
=20
> >> write ports and 2 read ports, each cell of which stores the port=20
> >> number which holds the latest write data.
> >>
> >> Example:
> >>
> >> simultaneously:
> >> Write through port 1 with address 3; --- no problem
> >>
> >> Write through port 0 with address 2;
> >>
> >> simultaneously:
> >> 0 --> LVT(2);
> >> 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cyc=
le?
> >>
> >> If above 2 simultaneously write operation are feasible, 2 read=20
> >> operations can read from LVT first to get proper port number, and then=
=20
> >> get the correct latest data read from the port number.
> >>
> >> Thank you.
> >>
> >> Weng
> >>
> >=20
> > Hi Weng,
> >=20
> > It is quite a simple scheme, assume you have 2 write ports each writing=
=20
> > into their own blockram. If port0 write to address 0x12 and port1 write=
s=20
> > to address 0x15 then the LVT (single bit array in this case) will store=
=20
> > array[12]=3D0 and array[15]=3D1.
> > Then if a read port read from address 15 the LVT array will set the mux=
=20
> > to 1 which connect the second blockram to the output.
> >=20
> > I use the XOR variant in my processor for a 8w8r block.
> >=20
> > Good luck,
> > Hans
> > www.ht-lab.com
> >=20
>=20
> Although the kicker with this paper is in simultaneous reads.  They=20
> gloss pretty hard over the fact that (per the end of 5.3 and 5.4), for N=
=20
> write ports and M read ports, you need N*M redundant BRAMs.  For their=20
> example of a 4-write, 8-read RAM they're using 32-fold the actual RAM=20
> requirements.  Can't even take advantage of BRAM packing, since they use=
=20
> both ports of each RAM to keep one dedicated write port and one=20
> dedicated read.  32x is a hell of a multiplier to be fighting against;=20
> it'll chew up all the RAM in a cheap FPGA before you can bat an eye.

I'm not sure what your point is.  That is the nature of multiport memories.=
  If you need it, you need it.  They can be the performance limiting portio=
n of a design and so they would be very welcome at nearly any cost. =20

I seem to recall when Xilinx block rams had true quad port capability in th=
at they could read and write from two ports all at the same time.  There ma=
y have only been two address buses, I can't recall.  But the two write port=
s could operate simultaneously.  The only limitation was both ports could n=
ot write to the same address.=20

  Rick C.

  -- Get 6 months of free supercharging
  -- Tesla referral code - https://ts.la/richard11209

On Tuesday, January 15, 2019 at 12:14:04 AM UTC-5, Rick C. Hodgin wrote:
> On Monday, January 14, 2019 at 7:01:55 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > On Monday, January 14, 2019 at 6:15:17 PM UTC-5, Rick C. Hodgin wrote:
> > > On Monday, January 14, 2019 at 5:42:37 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > > > Our patent seeking friend fails to understand the very basic issue
> > > > of how a multi-write port RAM can operate.
> > > 
> > > Always there with a pure heart of kindness, one given to teaching,
> > > apt to help compensate when someone is perhaps less than they should
> > > be.  Always accommodating, always uplifting, always at the ready to
> > > improve another's life, eh Rick?
> > 
> > I am happy to answer questions and provide advice to those who ask for it.  Sometimes the person finds it useful other times not.  I am not alone in offering the same sort of help to more than one person in this group.  But it is often declined presumably because the person asking for help doesn't really want help as much as getting others to do their work for them.  
> 
> Whoosh!

Are we trolling?  That is so un-Christian of you! 

  Rick C.

  -+ Get 6 months of free supercharging
  -+ Tesla referral code - https://ts.la/richard11209

On 14/01/2019 21:40, Weng Tianxiang wrote:
> On Monday, January 14, 2019 at 1:23:01 PM UTC-8, HT-Lab wrote:
>> On 14/01/2019 19:54, Weng Tianxiang wrote:
>>> Hi,
>>>
>>> I cannot understand the following paper:
>>> "Efficient Multi-Ported Memories for FPGAs"
>>>
>>> http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf
>>>
>>> FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write port and each of 2 blocks can be read individually by 2 different read.
>>>
>>> The paper essence for 2 write ports and 2 read ports is:
>>> There are 2 memory blocks each having 1 write port and 2 read ports.
>>>
>>> The 2 memory blocks provide 2 write ports to write independently.
>>>
>>> There is another memory block, called LVT (Live Value Table), with 2 write ports and 2 read ports, each cell of which stores the port number which holds the latest write data.
>>>
>>> Example:
>>>
>>> simultaneously:
>>> Write through port 1 with address 3; --- no problem
>>>
>>> Write through port 0 with address 2;
>>>
>>> simultaneously:
>>> 0 --> LVT(2);
>>> 1 --> LVT(3); --- how can it write 2 cells of a memory at the same cycle?
>>>
>>> If above 2 simultaneously write operation are feasible, 2 read operations can read from LVT first to get proper port number, and then get the correct latest data read from the port number.
>>>
>>> Thank you.
>>>
>>> Weng
>>>
>>
>> Hi Weng,
>>
>> It is quite a simple scheme, assume you have 2 write ports each writing
>> into their own blockram. If port0 write to address 0x12 and port1 writes
>> to address 0x15 then the LVT (single bit array in this case) will store
>> array[12]=0 and array[15]=1.
>> Then if a read port read from address 15 the LVT array will set the mux
>> to 1 which connect the second blockram to the output.
>>
>> I use the XOR variant in my processor for a 8w8r block.
>>
>> Good luck,
>> Hans
>> www.ht-lab.com
> 
> Hi Hans,
> 
> "If port0 write to address 0x12 and port1 writes
> to address 0x15 then the LVT (single bit array in this case) will store
> array[12]=0 and array[15]=1. "
> 
> How do you do: 0 --> array[12], 1 --> array[15] on the same cycle?
> 
Hi Weng,

The LVT array is not a blockram but just a bank of FF's, so you can set 
multiple bits at the same time.

Regards,
Hans.



> Thank you.
> 
> Weng
> 

Hi,

Here is my perfect answer to my question in VHDL and it has one copy and is capable for doing N writes and N reads at the same time:

signal R0, R1, ..., Rn_1 : std_logic_vector(BITS-1 downto 0);
  type NR_NW_TYPE : (0 to N-1) of unsigned(BITS-1 downto 0);
alias NR_NW : NR_NW_TYPE := (R0, R1, ..., Rn_1);

Now one can do N writes to any data and N reads from any data of NR_NW on the same cycle.

   A1 <= NR_NW(j); --> A1 <= Rj;

   NR_NW(j) <= B1; --> Rj <= B1;

Weng