Amount of wire and logic

Dear

Since Xilinx does not report wire utilization and technology data, I
expect that

Given FPGA device family :
(1) There is a constant ratio of INTERCONNECT to LOGIC.
(2) When amount of LOGIC increases N times, amount of INTERCONNECT
increases N times.

For example :
Virtex-II Pro-20 contains 9280 slices and Virtex-II Pro-100 contains
44096 slices.
That is, Virtex-II Pro-100 contains 4.7 times more slices.

It implies that :
In order to realize same ratio of INTERCONNECT to LOGIC,
Virtex-II Pro-100 contains 4.7 times more interconnect than Virtex-II
Pro 20.

I guess that :
The 'AREA' of INTERCONNECT for Virtex--II Pro 100 is MORE THAN 4.7
times larger than Virtex-II Pro.

Question is that
Is the AREA of INTERCONNECT for Virtex--II Pro 100 is 4.7 times larger
than Virtex-II Pro?

On Fri, 10 Aug 2007 04:15:09 -0700, Pasacco <pasacco@gmail.com> wrote:

>Dear
>
>Since Xilinx does not report wire utilization and technology data, I
>expect that
>
>Given FPGA device family :
>(1) There is a constant ratio of INTERCONNECT to LOGIC.
>(2) When amount of LOGIC increases N times, amount of INTERCONNECT
>increases N times.
>
>For example :
>Virtex-II Pro-20 contains 9280 slices and Virtex-II Pro-100 contains
>44096 slices.
>That is, Virtex-II Pro-100 contains 4.7 times more slices.
>
>It implies that :
>In order to realize same ratio of INTERCONNECT to LOGIC,
>Virtex-II Pro-100 contains 4.7 times more interconnect than Virtex-II
>Pro 20.
>
>I guess that :
>The 'AREA' of INTERCONNECT for Virtex--II Pro 100 is MORE THAN 4.7
>times larger than Virtex-II Pro.
>
>Question is that
>Is the AREA of INTERCONNECT for Virtex--II Pro 100 is 4.7 times larger
>than Virtex-II Pro?

I think the logic here is flawed.

If there are N elements, and the interconnect is intended to connect
form any of the N elements to another of the N elements, then:

if N grows, say it becomes k*N
then the M interconnecting elemtns should grow to k*k*M

This should not be taken as excat, but it seems to me that the
interconnections don't fgrow lineraly with the logic elements.

Regrads,

Zara

It means....
AREA of interconnects grows super-linearly, as AREA of logic linearly
grows.
Thank you

"Zara" <yozara@terra.es> wrote in message 
news:qgpob39hh31u3kfgmemeqashaq4p2hqa44@4ax.com...
> On Fri, 10 Aug 2007 04:15:09 -0700, Pasacco <pasacco@gmail.com> wrote:
>
<snip>
>
> I think the logic here is flawed.
>
> If there are N elements, and the interconnect is intended to connect
> form any of the N elements to another of the N elements, then:
>
> if N grows, say it becomes k*N
> then the M interconnecting elemtns should grow to k*k*M
>
> This should not be taken as excat, but it seems to me that the
> interconnections don't fgrow lineraly with the logic elements.
>
> Regrads,
>
> Zara

I think your logic here is flawed as well.

The local interconnections for each new CLB are replicated (OMUX, DOUBLE, 
even HEX).  The long lines are simply extended though one can look at each 
CLB having attibuting the X and Y pitch to the next CLB of additional copper 
for these as well.  The high end in a family shouldn't have more resources 
local to the CLB than the low end of the family, otherwise the software to 
select the routing could get pretty involved as devices are changed within a 
family.

The possible destinations increase for each source as the part gets larger, 
but the structure is still similar around each CLB regardless of size.

- John_H 

Everybody would agree that the need for interconnect grows faster than
the number of things to be interconnected. Ask any urban planner or
any phone company...
In FPGAs, the issue is both more complex and also much simpler:
More omplex:
The interconenct structure in any family consists of a wide varity of
different resources; direct connects, single, double, hex lines, long
lines, etc. This structure is highly optimized, and is revisited every
time we plan a new family. You cannot describe it with just one
number.
Much simpler:
Within a family, the ratio od routing to logic is practically
constant, mainly for softwarwe reasons.
One cannot create a completely new optimized software structure for
every chip size.

Fundamental routability, a big issue years ago, is hardly an issue
today.
Routing delays are, of course, still an issue, and will always be an
issue.
The basic elements in an FPGA can be as fast as the ones in the most
advanced dedicated chips and ASICs. It's the programmability that
slows down the FPGA, but programmability is also its greatest asset...
Peter Alfke



On Aug 10, 7:31 am, Pasacco <pasa...@gmail.com> wrote:
> It means....
> AREA of interconnects grows super-linearly, as AREA of logic linearly
> grows.
> Thank you

Pasacco,

I don't suppose that you have looked at using FPGA_EDITOR?

It would answer your question.

Austin

(P.S. I am always amused at how people 'discover' that FPGA design is
not some 'trivial task'... evidenced by the many who have tried to get
into the business, and then failed.)

"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1186763205.288969.56400@x35g2000prf.googlegroups.com...
> Everybody would agree that the need for interconnect grows faster than
> the number of things to be interconnected. Ask any urban planner or
> any phone company...
>
>
Are you sure about that Peter? I'm sure each house has one telephone wire to 
the exchange. All the complexity gets moved intot he exchange. So, wires are 
proportional to number of houses. Also, each house is on one road, has one 
electricity supply, one gas supply.

Cheers, Syms. 

Symon wrote:

> Are you sure about that Peter? I'm sure each house has one telephone wire to 
> the exchange. All the complexity gets moved intot he exchange. So, wires are 
> proportional to number of houses. Also, each house is on one road, has one 
> electricity supply, one gas supply.

If you want to connect two telephones, you'll need one wire. For three
telephone, you'll need a switch and 3 wires. For many more telephones,
you'll need a hierarchical system (in the beginning the telephone number
digits itself designated the different levels of the hierarchy), if you
don't want to connect each telephone with each other. This needs more wires
than endpoints, maybe a logarithmic number of additional wires per
endpoint, or maybe even more, if you want to handle many parallel
connections (I'm not a telephone expert), in addition to the wires from the
endpoints, but it doesn't increase proportional.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Analogies often are misleading.
The telephone system draws a big benefit from the fact that not
everybody wants to talk to everybody else  at the same time. (Remember
Mr Erlang?) And: a crossbar switch is really a humungously large
number of interconnects stuffed in a little box (and nowadays often
time-division multiplexed.)

The electricity-gas-water-sewer connections are non-individualized
unidirectional busses.

The analogy of urban planning may be more general and more
applicable...
Peter Alfke

On Aug 10, 11:18 am, Frank Buss <f...@frank-buss.de> wrote:
> Symon wrote:
> > Are you sure about that Peter? I'm sure each house has one telephone wire to
> > the exchange. All the complexity gets moved intot he exchange. So, wires are
> > proportional to number of houses. Also, each house is on one road, has one
> > electricity supply, one gas supply.
>
> If you want to connect two telephones, you'll need one wire. For three
> telephone, you'll need a switch and 3 wires. For many more telephones,
> you'll need a hierarchical system (in the beginning the telephone number
> digits itself designated the different levels of the hierarchy), if you
> don't want to connect each telephone with each other. This needs more wires
> than endpoints, maybe a logarithmic number of additional wires per
> endpoint, or maybe even more, if you want to handle many parallel
> connections (I'm not a telephone expert), in addition to the wires from the
> endpoints, but it doesn't increase proportional.
>
> --
> Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de

Peter Alfke wrote:

> Analogies often are misleading.
> The telephone system draws a big benefit from the fact that not
> everybody wants to talk to everybody else  at the same time. (Remember
> Mr Erlang?) And: a crossbar switch is really a humungously large
> number of interconnects stuffed in a little box (and nowadays often
> time-division multiplexed.)

That's true, but it is still a hierarchical system, which needs more wires
than endpoints, with switchers at the different levels, which can route to
higher levels, if needed:

http://en.wikipedia.org/wiki/Public_switched_telephone_network

So it is not proportional to the number of endpoints, but the additional
effort may be small with time multiplexed signals etc.

I wonder if some of these technics could be used for FPGAs as well. There
are some designs which doesn't need full speed interconnects and there are
designs with loose coupled parts over the chip (but each part could have a
high interconnection factor). So e.g. if one part of the chip needs to
transfer x bits of data to another part, it could be serialized and even
time multiplexed on a global internal bus system.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de