Amount of wire and logic

Pasacco wrote:
>>> (2) Number of wires grows over "g^1.5",
>>> ==> How did you obtain the value '1.5' ?
>> This is the result of Rents expirments in the 60ies. They have been
>> verified many
>> times in later experiments, also for FPGAs.
>> Kolja Sulimma
> 
> 
> Hi again :)
> I would like to ask two more things.
> 
> 1.
> I am looking for literature about :
> How to obtain the "growth rate of number of wires".
> For example, 1.5 or 1.2 or 1.6....
> 
> Could you please provide a pointer?
> (for example, book, paper, web, ....)

A good source with some reference to Rent's rule may be:
@techreport{ dehon96reconfigurable,
    author = "Andre' DeHon",
    title = "Reconfigurable Architectures for General-Purpose Computing",
    number = "AITR-1586",
    pages = "368",
    year = "1996",
    url = "citeseer.ist.psu.edu/dehon96reconfigurable.html" }



> 
> 2.
> I would like to obtain p value.
> Again, if you have pointer, please let me know.
> 
> Method that I have in mind is that:
> In FPGA Editor, simply count number of wires between neighbor CLBs.
> 

Pasacco wrote:
> Hi again :)
> I would like to ask two more things.
> 
> 1.
> I am looking for literature about :
> How to obtain the "growth rate of number of wires".
> For example, 1.5 or 1.2 or 1.6....
> 
> Could you please provide a pointer?
> (for example, book, paper, web, ....)
> 
> 2.
> I would like to obtain p value.
> Again, if you have pointer, please let me know.
> 
> Method that I have in mind is that:
> In FPGA Editor, simply count number of wires between neighbor CLBs.
> 

These things are general observations and tendencies. Much like Moore's 
law, there is no hard science behind them: they just turn out that way due 
to engineering/marketing/economic/etc. reasons.

For FPGAs, routing resources are simply scaled to compromise between the 
routability and performance targets requested by customers, 
manufacturability, engineering mindset, company policies, marketing spin, 
expected market developments and countless other variables.

If synthesis tools reported unused wires, I bet many FPGA customers would 
start complaining about the cost of having so much "dead copper" even in 
fully routed FPGAs... I bet current designs use far less than 25% of all 
routing and this figure actually sinks as devices scale up.