Amount of wire and logic

----------------------------
1. The high end in a family shouldn't have more resources
local to the CLB than the low end of the family.

==>
This means that "how INTERCONNECT is organized" is the same, within
same device family.
I opend FPGA EDITOR. The CLB structure 'looks' same, for different
device, within same family.


2. Everybody would agree that the need for interconnect grows faster
than
the number of things to be interconnected.

==>
This means that AREA of interconnects grows super-linearly, as AREA of
logic linearly
grows.
----------------------------

If yes, my first impression is that :
High-end device in a family provides "DECREASED ROUTABILITY" than low-
end device in a family.

For example, Virtex-II Pro-100 will provide "DECREASED ROUTABILITY"
than Virtex-II Pro-20.

Because:
(1) Maximum fan-out that a single wire can drive is 'constant' for
different devices.
(2) As device size increases, there will be decreased amount of "long
distance" wires, when wires are used up for neighbor logics.

What do you want to achieve with these theoretical considerations?
As I said, routability is not the problem anymore ..
And why do you use 5-year old examples (Virtex-2Pro?)
I prefer to address real problems using today's devices...
Peter Alfke
>


> If yes, my first impression is that :
> High-end device in a family provides "DECREASED ROUTABILITY" than low-
> end device in a family.
>
> For example, Virtex-II Pro-100 will provide "DECREASED ROUTABILITY"
> than Virtex-II Pro-20.
>
> Because:
> (1) Maximum fan-out that a single wire can drive is 'constant' for
> different devices.
> (2) As device size increases, there will be decreased amount of "long
> distance" wires, when wires are used up for neighbor logics.

On 10 Aug., 18:26, Peter Alfke <pe...@xilinx.com> wrote:
> Everybody would agree that the need for interconnect grows faster than
> the number of things to be interconnected. Ask any urban planner or
> any phone company...

This is known as Rent's rule
http://en.wikipedia.org/wiki/Rent%27s_Rule

It states essentially that between two portions of the chip that
contain g gates you
should have T=t*g^p wires.
The constants t and p depent on the design.
p is typically between 0.5 and 0.8.
As  a result the number of wires grows at a rate of somewhat over
g^1.5 and the area
of the wires (because the avarage length is g^0.5) grows faster than
g^2


> Much simpler:
> Within a family, the ratio od routing to logic is practically
> constant, mainly for softwarwe reasons.
> One cannot create a completely new optimized software structure for
> every chip size.
The pathfinder algorithm can cope pretty well with arbitrary networks.
However the network needs to be good enough that the placer can
assume a decent cost metric.

I did not closely look at the routing architecture for the newer
architectures
but in the 90s one could clearly see in the FPGA editor that the numer
of
wires (especially longlines) per routing channel increased with the
size
of the chip. This is regular enough that any routing algorithm should
be
able to cope with it.

> Fundamental routability, a big issue years ago, is hardly an issue
> today.
That is a  marketing decision, isn't it?

An FPGA with good routability is more expensive than an FPGA with
bad routability. Therefore early FPGAs were wire starved because it
economically makes more sense to make good use of the wires and
throw away some LUTs that can not be connected.

However as the wires are next to invisible to the designer, everybody
kept complaining that not all LUTs could be connected in a larger
XC4K.
People perceive that as a loss. Therefore all manufacturers switched
theire paradigm and added more of those expensive wires.
Now all LUTs can be used but the wire utilization is really low.

The good side of this is, that the tool runtime inproves a lot if
routing
is easy and the performance results are more predictable. But we
pay a price.

Kolja Sulimma

It is interesting to see the Rent's rule.

You can help me better understand the relationship.

For example, suppose :
Xilinx FPGA has a regular structure of CLBs.
Each CLB contains one SWITCH BOX and 4 SLICEs.
Each SLICE has approximately 40 pins.
Each CLB has approximately 400 pins.

Consider, device 1 has 100 CLBs and device 2 has 10000 CLBs.

According to your posting:
Device 2 is supposed to have "100^1.5" times more wires than device 1.
Device 2 is supposed to have "100^2" more area than device 1.
Am I understanding correctly?

It was mentioned that:
--------------------------------------------------------------
Number of wires grows at a rate of somewhat over  g^1.5 and the area
of the wires (because the  avarage length is g^0.5) grows faster than
g^2
--------------------------------------------------------------

Could you please explain why :

(1) Average length is "g^0.5",
==> Does this 'length' mean by "wire length" ?
       How did you obtain the value '0.5' ?

(2) Number of wires grows over "g^1.5",
==> How did you obtain the value '1.5' ?

(3) Area of wires grows faster than "g^2" ?
==> How did you obtain the value '2' ?

It will be appreciated if you provide some example :).
Thank you very much.

Pasacco, you are mixing up two things: Renz' rule, and real FPGAs
A real FPGA family does not span a 100-to-one size ratio. Usually just
10-to-1.
In Xilinx FPGAs, the area is roughly proportional to the number of
CLBs or Slices or LUTs, pick your preferred measurement. This picture
gets more complex due to the large number of non-CLB elements (BRAMs,
I/O, multipliers, CPUs etc.) that also populate the FPGA. And play a
very important role in making the FPGA fast, efficient, and
competitive.
I assume yours is a theoretical discussion...
Peter Alfke


On Aug 15, 10:14 am, Pasacco <pasa...@gmail.com> wrote:
> It is interesting to see the Rent's rule.
>
> You can help me better understand the relationship.
>
> For example, suppose :
> Xilinx FPGA has a regular structure of CLBs.
> Each CLB contains one SWITCH BOX and 4 SLICEs.
> Each SLICE has approximately 40 pins.
> Each CLB has approximately 400 pins.
>
> Consider, device 1 has 100 CLBs and device 2 has 10000 CLBs.
>
> According to your posting:
> Device 2 is supposed to have "100^1.5" times more wires than device 1.
> Device 2 is supposed to have "100^2" more area than device 1.
> Am I understanding correctly?
>
> It was mentioned that:
> --------------------------------------------------------------
> Number of wires grows at a rate of somewhat over  g^1.5 and the area
> of the wires (because the  avarage length is g^0.5) grows faster than
> g^2
> --------------------------------------------------------------
>
> Could you please explain why :
>
> (1) Average length is "g^0.5",
> ==> Does this 'length' mean by "wire length" ?
>        How did you obtain the value '0.5' ?
>
> (2) Number of wires grows over "g^1.5",
> ==> How did you obtain the value '1.5' ?
>
> (3) Area of wires grows faster than "g^2" ?
> ==> How did you obtain the value '2' ?
>
> It will be appreciated if you provide some example :).
> Thank you very much.

First of all:
Peters observation is correct. While even for a dynamic of 10:1 you
should have more wires
per routing channel, you do not see much of that in real fpgas for
practical reason.
A regular structure is simpler to design, test, write software for,
etc.
So I expect Xilinx to design the routing based on the requirements of
the large parts.
Maybe a little on the short side. This means that the small devices
have more wires
than needed. But as yield is an exponential function of size the
economic impact
of extra wires is not as important for smaller devices.

However in some families you seed routing structures that only appear
for larger devices.
For example in Coolrunner the macrocells are grouped. The smallest
device has only one group
(dont remember the name of the group in Xilinx Lingo) with routing in
the group.
The next device has two groups, plus routing between them.

Some families of some vendors increase the number of wires in all
routing channels for larger devices
or add an additional long distance routing ressource in the center of
the FPGA for larger devices.

Were you see rents rule in action is the design of the routing
hierarchy of a single FPGA.
Count the number of terminals of a Slice, of a CLB, of all CLBs
connected to the same switchbox,
of a clock region, of a half FPGA, of the whole FPGA. It is likely to
grow roughly at the expected rate.

On Aug 15, 7:14 pm, Pasacco <pasa...@gmail.com> wrote:

> For example, suppose :
> Xilinx FPGA has a regular structure of CLBs.
> Each CLB contains one SWITCH BOX and 4 SLICEs.
> Each SLICE has approximately 40 pins.
> Each CLB has approximately 400 pins.
>
> Consider, device 1 has 100 CLBs and device 2 has 10000 CLBs.
>
> According to your posting:
> Device 2 is supposed to have "100^1.5" times more wires than device 1.
> Device 2 is supposed to have "100^2" more area than device 1.
> Am I understanding correctly?

Yes, were roughly.
The better formulation is: A design in the large device is expected to
use about that much
more wires than a typical design in a large device. The manufacturer
might chose to
deviate from that for other reasons.
Also, this is a typical value. Designs vary. A smith-waterman pattern
matcher has a rent exponent of
0, so does an SRAM.

> It was mentioned that:
> --------------------------------------------------------------
> Number of wires grows at a rate of somewhat over  g^1.5 and the area
> of the wires (because the  avarage length is g^0.5) grows faster than
> g^2
> --------------------------------------------------------------
>
> Could you please explain why :
>
> (1) Average length is "g^0.5",
> ==> Does this 'length' mean by "wire length" ?
>        How did you obtain the value '0.5' ?

What is the maximum distance in a chip with 100 LUTs laid out as a
square?
What is the maximum distance in a chip with 10000 LUTs laid out as a
square?

> (2) Number of wires grows over "g^1.5",
> ==> How did you obtain the value '1.5' ?
This is the result of Rents expirments in the 60ies. They have been
verified many
times in later experiments, also for FPGAs.
Actually Rent counted terminals, but the wires are roughly
proportional to terminals
because must wires have a very low number of terminals on them.

> (3) Area of wires grows faster than "g^2" ?
> ==> How did you obtain the value '2' ?

Number of wires times length of wires...

Kolja Sulimma

Kolja Sulimma

Now I better understand.
Number of wires grows faster than number of logic, though the "growth
rate" in state-of-the-art FPGA  device is not that high.
Thank you for providing a good example.

> > (2) Number of wires grows over "g^1.5",
> > ==> How did you obtain the value '1.5' ?
>
> This is the result of Rents expirments in the 60ies. They have been
> verified many
> times in later experiments, also for FPGAs.
>
> Kolja Sulimma

Hi again :)
I would like to ask one thing.
I am looking for literature about :
how to obtain the "growth rate of number of wires".

For example, 1.5 or 1.2 or 1.6....

Could you please provide a pointer?
(for example, book, paper, web, ....)

> > (2) Number of wires grows over "g^1.5",
> > ==> How did you obtain the value '1.5' ?
>
> This is the result of Rents expirments in the 60ies. They have been
> verified many
> times in later experiments, also for FPGAs.
> Kolja Sulimma


Hi again :)
I would like to ask two more things.

1.
I am looking for literature about :
How to obtain the "growth rate of number of wires".
For example, 1.5 or 1.2 or 1.6....

Could you please provide a pointer?
(for example, book, paper, web, ....)

2.
I would like to obtain p value.
Again, if you have pointer, please let me know.

Method that I have in mind is that:
In FPGA Editor, simply count number of wires between neighbor CLBs.

On Aug 20, 7:18 pm, Pasacco <pasa...@gmail.com> wrote:
>
> Method that I have in mind is that:
> In FPGA Editor, simply count number of wires between neighbor CLBs.

Good idea:
Do something, instead of just asking repetitive questions...
Peter Alfke