GSR in Spartan3 ?

Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote:

: "Symon" <symon_brewer@hotmail.com> wrote in message
: news:c0rrgi$1b7t8e$1@ID-212844.news.uni-berlin.de...
: >
: > > So what do I need to do to get 'rst' connected to the GSR
: > > net?
: > >
: > > I've spent a fair bit of time searching the Xilinx site/docs
: > > and googling this group with no results. It seems to be one
: > > of those things that I should probably know, but just can't
: > > find anywhere.
: > >
: > > Thanks for any pointers,
: > >
: > > Nial.
: > >
: > Hi Nial,
: > Can you instantiate the STARTBUF_SPARTAN3 design element? Listed under
: > STARTBUF_architecture in the Design Elements section of the Libraries
: guide.
: > Cheers mate, Syms.


: Symon, that doesn't do it.

: The STARTUP_SPARTAN3 module allows you to drive the GSR net from
: an user defined source but this reset mechanism isn't visible to
: HDL so simulations won't work.

: The STARTBUF_SPARTAN3 module does the same thing, but with an
: output you can connect to your HDL reset lines which mirrors
: the GSR net. Thus simulations should match real life.


: This doesn't help me tie my top level 'rst' net to the GSR.
: I've checked through my design and _all_ my asynch reset
: declarations use this net with the correct polarity.

have
  STARTUP_SPARTAN2 rst (.GSR(grst));

in the top level module

Use grst where you need it:
   always @ (posedge rclk or posedge grst)
     if (grst)
       rdo_cnt <= 20'h0;
     else if (!rdo_rr)
       rdo_cnt <= rdolen;
     else if ( rdo_rr)
       rdo_cnt <= rdo_cnt-1;

Drive the reset in your test fixure

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote
in message news:c0vllm$d35$1@news.tu-darmstadt.de...

> : This doesn't help me tie my top level 'rst' net to the GSR.
> : I've checked through my design and _all_ my asynch reset
> : declarations use this net with the correct polarity.
>
> have
>   STARTUP_SPARTAN2 rst (.GSR(grst));
>
> in the top level module
>
> Use grst where you need it:
>    always @ (posedge rclk or posedge grst)
>      if (grst)
>        rdo_cnt <= 20'h0;
>      else if (!rdo_rr)
>        rdo_cnt <= rdolen;
>      else if ( rdo_rr)
>        rdo_cnt <= rdo_cnt-1;
>
> Drive the reset in your test fixure

I can't drive it, it's not a top level port.

When I described 'rst' as a top level net, it's not
actually a port on the top level design. The chip
I'm designing for doesn't have an external reset
input pin.

My understanding is that STARTUP_SPARTAN2/3 is
used to allow a top level reset input to drive
the GSR net, but this isn't what I need.

I want the synthesis tool to drive my rst with
the GSR net.

Nial

ROC is a place holder and simulation primitive.  It should appear in
your edif netlist, then the xilinx mapper removes it and connects the
net to GSR.  It is doing what you want.  You can check the xilinx
results in FPGA editor to convince yourself.

Nial Stewart wrote:

> > Thanks Lars, I've implemented the reset count as discussed with
> > John earlier. This looks cleaner though so I'll try it tomorrow
> > and report back results.
>
> Hmm.
>
> I've tried using the ROC component as Lars suggested. The syntheis
> report doesn't give many clues as to what's going on, it says...
> "Generating a Black Box for component <ROC>"
>
> ... which might be expected, but rst or GSR aren't mentioned.
>
> The map report says ...
>
> The trimmed logic reported below is either:
>    1. part of a cycle
>    2. part of disabled logic
>    3. a side-effect of other trimmed logic
>
> The signal "roc_inst_1" is unused and has been removed.
>
> Optimized Block(s):
> TYPE   BLOCK
> GND   XST_GND
> VCC   XST_VCC
> BUF   roc_inst_1
> BUF   roc_inst_2
>
> ...which might suggest that ROC has been replaced with
> something else (ie a connection to the GSR net) but
> it doesn't explicitly state this.
>
> Can anyone confirm that this means the ROC component has been
> removed and the rst net has been connected to GSR?
>
> If I can't get this confirmed I'll stick with the startup
> counter.
>
> Time for an experiment with a SpartanII I think.
>
> Nial.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote:

: "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote
: in message news:c0vllm$d35$1@news.tu-darmstadt.de...

: > : This doesn't help me tie my top level 'rst' net to the GSR.
: > : I've checked through my design and _all_ my asynch reset
: > : declarations use this net with the correct polarity.
: >
: > have
: >   STARTUP_SPARTAN2 rst (.GSR(grst));
: >
: > in the top level module
: >
: > Use grst where you need it:
: >    always @ (posedge rclk or posedge grst)
: >      if (grst)
: >        rdo_cnt <= 20'h0;
: >      else if (!rdo_rr)
: >        rdo_cnt <= rdolen;
: >      else if ( rdo_rr)
: >        rdo_cnt <= rdo_cnt-1;
: >
: > Drive the reset in your test fixure

: I can't drive it, it's not a top level port.

: When I described 'rst' as a top level net, it's not
: actually a port on the top level design. The chip
: I'm designing for doesn't have an external reset
: input pin.

: My understanding is that STARTUP_SPARTAN2/3 is
: used to allow a top level reset input to drive
: the GSR net, but this isn't what I need.

Any logic signal can drive the .GSR input of the STARTUP_SPARTANX. You can
generate it internally or connect to an external pin. Where's the problem?

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

> Any logic signal can drive the .GSR input of the STARTUP_SPARTANX. You can
> generate it internally or connect to an external pin. Where's the problem?


I don't want to have to drive it. GSR is driven as part of the
power up process and I want this to drive my reset net.

Previously using Leonardo I've been able to have a reset
net declared as a signal with some directives to tell
Leonardo to connect this net to the GSR.

I was hoping that XST would do the same thing, but it doesn't
seem to. As I said elsewhere in the thread Simplify has a
directive "xc_isgsr" which looks like it's doing this, but
there's no equivalent XST dierective listed.



Nial.

Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote:
: > Any logic signal can drive the .GSR input of the STARTUP_SPARTANX. You can
: > generate it internally or connect to an external pin. Where's the problem?


: I don't want to have to drive it. GSR is driven as part of the
: power up process and I want this to drive my reset net.

: Previously using Leonardo I've been able to have a reset
: net declared as a signal with some directives to tell
: Leonardo to connect this net to the GSR.

: I was hoping that XST would do the same thing, but it doesn't
: seem to. As I said elsewhere in the thread Simplify has a
: directive "xc_isgsr" which looks like it's doing this, but
: there's no equivalent XST dierective listed.


You can access glbl.GSR in you testbench...

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

"Ray Andraka" <ray@andraka.com> wrote in message
news:40336236.A85B6B7F@andraka.com...
> ROC is a place holder and simulation primitive.  It should appear in
> your edif netlist, then the xilinx mapper removes it and connects the
> net to GSR.  It is doing what you want.  You can check the xilinx
> results in FPGA editor to convince yourself.


Thanks Ray, this was the confirmation I was looking for.

Previously I think the reset net had to reset _all_ flip
flops in the design for the synthesis tools to pick it up
and connect it to GSR.

Do you know if these conditions still apply if using ROC?


I had looked in FPGA editor, but am not _that_ familiar with
it and wasn't sure what it was telling me.

Time to read the tutorial.


Thanks again,

Nial.

> You can access glbl.GSR in you testbench...

But what about in real life, which is what I'm
worried about.

The STARTUP_SPARTAN3 only has an input port,
this is used to drive GSR.

I need something to drive my reset net, ie
GSR -> rst.


Nial.

Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote:
: > You can access glbl.GSR in you testbench...

: But what about in real life, which is what I'm
: worried about.

: The STARTUP_SPARTAN3 only has an input port,
: this is used to drive GSR.

Inn real life, GSR is driven when the FPGA boots. For simulation you drive
or force it. Wher's the problem?

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in
message news:40337c46$0$8980$fa0fcedb@lovejoy.zen.co.uk...
>
> > ROC is a place holder and simulation primitive.  It should appear in
> > your edif netlist, then the xilinx mapper removes it and connects the
> > net to GSR.  It is doing what you want.  You can check the xilinx
> > results in FPGA editor to convince yourself.

> I had looked in FPGA editor, but am not _that_ familiar with
> it and wasn't sure what it was telling me.
>
> Time to read the tutorial.


I've built the design with the ROC module driving rst.

In the floorplanner if I do a search for Net rst, highlight it then
look for all logic loading that net I get 491 flip flops.
There are 1372 slice flip-flops in the design, and many that
aren't loading rst are asynchronously reset in the code.
You can easily find flip flos in the floor plan that aren't
selected.

I'm not happy this is doing what I want it to.


When I use the counter reset mechanism as discussed
elsewhere in the thread and do a search for rst I
get 15 nets. Selecting these and doing a search for
then selecting logic loading these nets gives 1558 symbols,
and I can't see a flip_flop on the floorplan that's
not selected.

I'll stick with this method unless I can work out why
the GSR implementation isn't working.


Did Ray actually give advice that was wrong?

>:-0



Nial.