Which to learn: Verilog vs. VHDL?

On Tue, 15 Apr 2008 14:15:25 -0400, Fei Liu <fei.liu@gmail.com> wrote:

>Michael wrote:
>> Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter
>> Kit with Xilinx ISE. I am an electrical engineer by training and did
>> some verilog in my collegiate days - but that was quite some time ago
>> and it is all very fuzzy now. I have decided that as an EE I should be
>> familiar with FPGAs - so I'm re-educating myself. With that said -
>> which would be more useful to learn in the industrial world: Verilog
>> or VHDL?
>> 
>> Thanks!
>> 
>> -Michael
>
>I personally found verilog very intuitive with my software engineering 
>background. VHDL on the other hand seems weird to me. YMMY.

I personally found both Verilog and C very weird, with my software engineering
background. VHDL on the other hand seems much better designed, like Modula-2.
YMMV.

- Brian

>> which would be more useful to learn in the industrial world: Verilog
>> or VHDL?
> 
> In Europe (including UK) VHDL is more commonly used.
> 
> In USA Verilog is prevalent.

The studies I have seen were on $$$ spent on EDA tools which seems
to show that people pay more money for Verilog tools.
Some liked Verilog bigots liked to imply this correlated to users.

For a rough order of measure of users, I look at Monster and based on
rough data (not removing VHDL companies advertising also for
Verilog coders and vice versa), there is a even split of
VHDL and Verilog in the US market.

Do you have a more accurate measure?

Cheers,
Jim

Michael,
You might consider the industry you are interested in and research
the companies that you may wish to work for and see what they use.
This will give you the best idea as to which to learn first.

Cheers,
Jim

> Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter
> Kit with Xilinx ISE. I am an electrical engineer by training and did
> some verilog in my collegiate days - but that was quite some time ago
> and it is all very fuzzy now. I have decided that as an EE I should be
> familiar with FPGAs - so I'm re-educating myself. With that said -
> which would be more useful to learn in the industrial world: Verilog
> or VHDL?
> 
> Thanks!
> 
> -Michael

it is all very fuzzy now. http://www.hqew.net/product-data/LM317T

On 12/28/2012 3:28 AM, joey899244@yahoo.cn wrote:
> it is all very fuzzy now. http://www.hqew.net/product-data/LM317T

I don't think there is any discussion that Verilog is easier to learn 
than VHDL.  As to which is the better language to learn is often 
debated.  I would say that the choice of language would depend on your 
goals for learning the language.  If you are doing hobby work, then you 
will have to choose yourself.  If you want to get work in the field, I 
would say learn both as there are lots of each, but most employers 
prefer one or the other.  I think if you learn VHDL first, Verilog will 
feel like a breath of fresh air... lol

That's my advice.  Meanwhile I am working with VHDL and have never put 
much effort into learning Verilog because I can't find a good book to 
use as a reference and learning guide.  I'm told none of the Verilog 
books are all that good.

There is also System Verilog and a number of other languages I  believe.

Rick

joey899244@yahoo.cn wrote:

> it is all very fuzzy now. http://www.hqew.net/product-data/LM317T

When I decided to learn verilog, I was told that C programmers find
verilog easier than VHDL. Still seems true to me.

For some time, the usual FPGA software had more support for
VHDL, but I think most now support both.

Also, for some time it seems that most ASIC work was done in verilog,
while more FPGA work done in VHDL. I don't know if that is still true.

I can usually read VHDL, but won't claim to be able to write it.

-- glen

On Fri, 28 Dec 2012 17:50:10 -0500, rickman wrote:

> On 12/28/2012 3:28 AM, joey899244@yahoo.cn wrote:
>> it is all very fuzzy now. http://www.hqew.net/product-data/LM317T
> 
> I don't think there is any discussion that Verilog is easier to learn
> than VHDL.  As to which is the better language to learn is often
> debated.  I would say that the choice of language would depend on your
> goals for learning the language.  If you are doing hobby work, then you
> will have to choose yourself.  If you want to get work in the field, I
> would say learn both as there are lots of each, but most employers
> prefer one or the other.  I think if you learn VHDL first, Verilog will
> feel like a breath of fresh air... lol
> 
> That's my advice.  Meanwhile I am working with VHDL and have never put
> much effort into learning Verilog because I can't find a good book to
> use as a reference and learning guide.  I'm told none of the Verilog
> books are all that good.
> 
> There is also System Verilog and a number of other languages I  believe.

I used Thomas & Moorby's "The Verilog Hardware Description Language", 
Fourth Edition.  It seemed to be OK.

Verilog vs. VHDL varies a lot by industry and region, as well as by 
company.  I chose Verilog because I live on the west coast, and most FPGA 
work around here is done in Verilog.  But the _second_ time I had to make 
money doing FPGA design, it was for an east coast company and they used 
VHDL.

So now I know both equally well.  (Or, more accurately, equally poorly).

-- 
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

Tim Wescott <tim@seemywebsite.com> wrote:

(snip on verilog vs. VHDL)

> I used Thomas & Moorby's "The Verilog Hardware Description Language", 
> Fourth Edition.  It seemed to be OK.
 
> Verilog vs. VHDL varies a lot by industry and region, as well as by 
> company.  I chose Verilog because I live on the west coast, and most FPGA 
> work around here is done in Verilog.  But the _second_ time I had to make 
> money doing FPGA design, it was for an east coast company and they used 
> VHDL.
 
> So now I know both equally well.  (Or, more accurately, equally poorly).

For even more fun, use both in the same project. Even more, add in some
AHDL and schematic capture at the same time. (Yes, I did that once.)

-- glen

On 12/28/2012 7:00 PM, Tim Wescott wrote:
> On Fri, 28 Dec 2012 17:50:10 -0500, rickman wrote:
>
>> On 12/28/2012 3:28 AM, joey899244@yahoo.cn wrote:
>>> it is all very fuzzy now. http://www.hqew.net/product-data/LM317T
>>
>> I don't think there is any discussion that Verilog is easier to learn
>> than VHDL.  As to which is the better language to learn is often
>> debated.  I would say that the choice of language would depend on your
>> goals for learning the language.  If you are doing hobby work, then you
>> will have to choose yourself.  If you want to get work in the field, I
>> would say learn both as there are lots of each, but most employers
>> prefer one or the other.  I think if you learn VHDL first, Verilog will
>> feel like a breath of fresh air... lol
>>
>> That's my advice.  Meanwhile I am working with VHDL and have never put
>> much effort into learning Verilog because I can't find a good book to
>> use as a reference and learning guide.  I'm told none of the Verilog
>> books are all that good.
>>
>> There is also System Verilog and a number of other languages I  believe.
>
> I used Thomas&  Moorby's "The Verilog Hardware Description Language",
> Fourth Edition.  It seemed to be OK.

I'm not sure how good "ok" is I guess.  I asked in the Verilog group for 
recommendations for a good book and several told me there were no "good" 
Verilog books.  I should pick up a good Verilog book sometime.  The only 
thing I have is a book that covers both VHDL and Verilog with many 
examples done in both languages.  I can't recall the name and I'm not 
sure the book is here at the moment.  One of the problems of having dual 
(or is it trinary) residency.  I expect my next text book will be an 
e-copy if I can get it without locking to hardware.  How does that work 
exactly?


> Verilog vs. VHDL varies a lot by industry and region, as well as by
> company.  I chose Verilog because I live on the west coast, and most FPGA
> work around here is done in Verilog.  But the _second_ time I had to make
> money doing FPGA design, it was for an east coast company and they used
> VHDL.
>
> So now I know both equally well.  (Or, more accurately, equally poorly).

Yes, I did some work for a networking company once.  I did my code in 
VHDL which they didn't mind since it was a self contained board.  But 
all of their work was Verilog which I got to see.  I found it less well 
documented and much poorer use of white space and formatting.  But much 
of that is just what you are used to I'm sure.  I don't think they 
suffered any great loss of productivity.

I believe there have been a few competitions where Verilog was shown to 
be a bit more productive in banging out code you can do in a few hours. 
  This is not the end all, be all of language comparisons however.  I'm 
sure the long term costs of writing code are not completely correlated 
to how quickly a few hundred lines of code can be written and debugged.

Rick

Le 29/12/2012 01:20, glen herrmannsfeldt a �crit :

> For even more fun, use both in the same project. Even more, add in some
> AHDL and schematic capture at the same time. (Yes, I did that once.)

You need to spend more money on the tools so that you can simulate this 
lot. That's expensive fun ;o)

Nicolas (who will probably very shortly need to learn Verilog)