Which to learn: Verilog vs. VHDL?

On Dec 29, 6:29=A0pm, Nicolas Matringe <nicolas.matri...@fre.fre> wrote:
> Le 29/12/2012 01:20, glen herrmannsfeldt a =E9crit :
>
> > For even more fun, use both in the same project. Even more, add in some
> > AHDL and schematic capture at the same time. (Yes, I did that once.)
>
> You need to spend more money on the tools so that you can simulate this
> lot. That's expensive fun ;o)
>

For small simulation of synthesizable design written in that wild mix,
you can simulate in internal simulator of QuartusII 9.1 Web edition.
Costs exactly 0 USD.

> Nicolas (who will probably very shortly need to learn Verilog)

"rickman"  wrote in message news:kbl7n3$c81$1@dont-email.me...
> I think if you learn VHDL first, Verilog will feel like a breath of fresh 
> air... lol

VHDL plays ADA to Verilog's "C"

On Mon, 31 Dec 2012 10:50:08 +0000, Andrew Holme wrote:

> "rickman"  wrote in message news:kbl7n3$c81$1@dont-email.me...
>> I think if you learn VHDL first, Verilog will feel like a breath of
>> fresh air... lol
> 
> VHDL plays ADA to Verilog's "C"

Yes, which is seriously one of VHDL's strong points.
(btw it's Ada not ADA, since it's a name not an acronym) 

I am increasingly finding the synergy between Ada and VHDL to be very 
useful. I can now use a high level language on both sides of the HW/SW 
divide, even for low-level programming on AVR or MSP430 processors, and 
(unless a customer specifically asks for C) no longer bother with the 
tedious debugging and poor productivity that a low level language like C 
used to give.

I have experimentally called Ada code from VHDL, and vice versa, using 
the minimal VHPIDirect interface available in GHDL. The fact that GHDL 
uses GCC, which has very good Ada support, makes this easy.
The link works both ways, but I haven't tried it with any other simulator.

This ought to allow me (when I get back to that project) to use the very 
clean object-oriented facilities of Ada-2005 to give the sort of 
constrained random test methodology that Janick Bergeron talks about in 
his "Writing Testbenches" book. It's not that I don't appreciate the OSVVM 
approach of doing it all in VHDL, but I believe that using inheritance 
and class extension allow much more reuse and faster test development.

- Brian

On Fri, 28 Dec 2012 17:50:10 -0500
rickman <gnuarm@gmail.com> wrote:
> 
> That's my advice.  Meanwhile I am working with VHDL and have never put 
> much effort into learning Verilog because I can't find a good book to 
> use as a reference and learning guide.  I'm told none of the Verilog 
> books are all that good.
> 

What Verilog I know I got from "Verilog by Example" by Blaine C.
Readler, which I thought was pretty good.  Then again, I write VHDL
pretty exclusively, and really only needed enough Verilog to be able to
suss out what other people were doing.

In terms of which language is "better", one of the things I've been
finding lately while I'm neck deep in Altera's tools is that, for
Altera at least, Verilog support is a given whereas VHDL support is
marginal at best.  A lot of their fancier tools are only available in
Verilog, or have glaring bugs in VHDL mode.  This means that, if you
write VHDL like I do, you're absolutely up a creek without a mixed
language simulator.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

On Tuesday, April 15, 2008 8:01:58 PM UTC-5, Eric Smith wrote:
> lm317t wrote:
> > The syntax for Verilog will be a bit more familiar to you if you
> > program in C/C++.
>=20
> Which is a drawback, not a benefit, since the actual langauge semantics
> are almost nothing like C.  The superficial similarity of the syntax
> seems to cause a lot of confusion for new Verilog designers.

I kinda agree with that statement, but it is relatively easy to get over th=
at hump. I started with Verilog a year ago after much experience with C. I =
was able to get up and running with Verilog in a short time (with the help =
of useful sample code that was close to what I was trying to do) while afte=
r about the same time spent with VHDL, I am nowhere as far along.
There is something with VHDL that makes it appear unfriendly to people with=
 C background. I started completely on my own with nobody to help me along,=
 but I found Verilog really friendly.
I do not have enough experience to say if one is superior to the other, but=
 since at some point you will probably have to know both, start with Verilo=
g, it is less off-putting.
For a plug (no financial interest, just a satisfied customer), look at the =
knjn.com kits and the related fpga4fun.com site. 

On Thursday, January 3, 2013 9:55:10 AM UTC-6, 4rt.dw...@gmail.com wrote:
> On Tuesday, April 15, 2008 8:01:58 PM UTC-5, Eric Smith wrote:
>=20
> > lm317t wrote:
>=20
> > > The syntax for Verilog will be a bit more familiar to you if you
>=20
> > > program in C/C++.
>=20
> >=20
>=20
> > Which is a drawback, not a benefit, since the actual langauge semantics
>=20
> > are almost nothing like C.  The superficial similarity of the syntax
>=20
> > seems to cause a lot of confusion for new Verilog designers.
>=20
>=20
>=20
> I kinda agree with that statement, but it is relatively easy to get over =
that hump. I started with Verilog a year ago after much experience with C. =
I was able to get up and running with Verilog in a short time (with the hel=
p of useful sample code that was close to what I was trying to do) while af=
ter about the same time spent with VHDL, I am nowhere as far along.
>=20
> There is something with VHDL that makes it appear unfriendly to people wi=
th C background. I started completely on my own with nobody to help me alon=
g, but I found Verilog really friendly.
>=20
> I do not have enough experience to say if one is superior to the other, b=
ut since at some point you will probably have to know both, start with Veri=
log, it is less off-putting.
>=20
> For a plug (no financial interest, just a satisfied customer), look at th=
e knjn.com kits and the related fpga4fun.com site.

On Thu, 3 Jan 2013 07:55:10 -0800 (PST)
4rt.dw8.5t4wr@gmail.com wrote:

> There is something with VHDL that makes it appear unfriendly to people with C background. I started completely on my own with nobody to help me along, but I found Verilog really friendly.

I think that "something" is verbosity.  C allows you to, and C
programmers seem to thrive on, writing extremely terse code.

  while (!(c = *cptr++)) {...}

sorts of things abound, and are considered to be both clever and
canonical.  VHDL doesn't want you to, and doesn't encourage you to, and
considers verbose code with lots of very explicit description of
what's going on, to be an asset rather than a waste of keystrokes.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

4rt.dw8.5t4wr@gmail.com wrote:
> On Tuesday, April 15, 2008 8:01:58 PM UTC-5, Eric Smith wrote:
>> lm317t wrote:
>> > The syntax for Verilog will be a bit more familiar to you if you
>> > program in C/C++.
 
>> Which is a drawback, not a benefit, since the actual langauge semantics
>> are almost nothing like C.  The superficial similarity of the syntax
>> seems to cause a lot of confusion for new Verilog designers.

No, that isn't it. 

For one, there are people using C as an HDL, which I don't find an
especially good idea. (At least for the kinds of things I want to do,
you can't port an algorithm from C code to HDL code.)

But VHDL seems to be verbose, especially in its declarations, in ways
that both C and verilog are not.

Both C and verilog use &, |, and ^ for and, or, and xor operators.
Maybe VHDL does, too. It is, though, fairly simple to learn to write
verilog expressions, that is, the right hand side of continuous
assignment statements, if you know C.
 
> I kinda agree with that statement, but it is relatively easy to 
> get over that hump. I started with Verilog a year ago after much 
> experience with C. I was able to get up and running with Verilog 
> in a short time (with the help of useful sample code that was 
> close to what I was trying to do) while after about the same time 
> spent with VHDL, I am nowhere as far along.

I don't know about others, but I generally write structural
verilog with continuous assignment, and mostly not behavioral
verilog, except for FF's (and state machines). Verilog has some
operators that C doesn't have, but it isn't so hard to learn those,
and they usually look like you might expect them to look like if
C did have them.

As well as I remember them, the VHDL operators are somewhat
different, and not easy for C programmers to remember.

> There is something with VHDL that makes it appear unfriendly to 
> people with C background. I started completely on my own with 
> nobody to help me along, but I found Verilog really friendly.
> I do not have enough experience to say if one is superior to the 
> other, but since at some point you will probably have to know both, 
> start with Verilog, it is less off-putting.

Yes. I bought two books (about 20 years ago, so there weren't all
that many choices) and with some synthesis tools and just started
writing. Maybe it wouldn't have taken so much longer with VHDL,
but it was pretty easy with verilog.

> For a plug (no financial interest, just a satisfied customer), 
> look at the knjn.com kits and the related fpga4fun.com site. 

-- glen

On Thu, 03 Jan 2013 17:27:14 +0000, glen herrmannsfeldt wrote:

> 4rt.dw8.5t4wr@gmail.com wrote:
>> On Tuesday, April 15, 2008 8:01:58 PM UTC-5, Eric Smith wrote:
>>> lm317t wrote:
>>> > The syntax for Verilog will be a bit more familiar to you if you
>>> > program in C/C++.
>  
>>> Which is a drawback, not a benefit, since the actual langauge
>>> semantics are almost nothing like C.  The superficial similarity of
>>> the syntax seems to cause a lot of confusion for new Verilog
>>> designers.
> 
> No, that isn't it.
> 
> For one, there are people using C as an HDL, which I don't find an
> especially good idea. (At least for the kinds of things I want to do,
> you can't port an algorithm from C code to HDL code.)
> 
> But VHDL seems to be verbose, especially in its declarations, in ways
> that both C and verilog are not.
> 
> Both C and verilog use &, |, and ^ for and, or, and xor operators. Maybe
> VHDL does, too. It is, though, fairly simple to learn to write verilog
> expressions, that is, the right hand side of continuous assignment
> statements, if you know C.
>  
>> I kinda agree with that statement, but it is relatively easy to get
>> over that hump. I started with Verilog a year ago after much experience
>> with C. I was able to get up and running with Verilog in a short time
>> (with the help of useful sample code that was close to what I was
>> trying to do) while after about the same time spent with VHDL, I am
>> nowhere as far along.
> 
> I don't know about others, but I generally write structural verilog with
> continuous assignment, and mostly not behavioral verilog, except for
> FF's (and state machines). Verilog has some operators that C doesn't
> have, but it isn't so hard to learn those, and they usually look like
> you might expect them to look like if C did have them.
> 
> As well as I remember them, the VHDL operators are somewhat different,
> and not easy for C programmers to remember.
> 
>> There is something with VHDL that makes it appear unfriendly to people
>> with C background. I started completely on my own with nobody to help
>> me along, but I found Verilog really friendly. I do not have enough
>> experience to say if one is superior to the other, but since at some
>> point you will probably have to know both, start with Verilog, it is
>> less off-putting.
> 
> Yes. I bought two books (about 20 years ago, so there weren't all that
> many choices) and with some synthesis tools and just started writing.
> Maybe it wouldn't have taken so much longer with VHDL, but it was pretty
> easy with verilog.
> 
>> For a plug (no financial interest, just a satisfied customer), look at
>> the knjn.com kits and the related fpga4fun.com site.

I have to admit, the biggest problem that I have as a C++ programmer when 
writing in either VHDL or Verilog is envy: in both (IIRC) VHDL or Verilog, 
when you have a module with a bazzilion input and output signals, you can 
invoke it with a syntax something like

module_name(module_signal_name = local_signal_name, ...)

In C++, when, for reasons of utility, you are forced to design a class 
whose constructor has a bazzilion inputs, you have to hold your breath, 
close your eyes, cross your fingers, and hope that whoever uses that 
constructor call gets all the right things in all the right places: I'd 
Much Rather be able to invoke the syntax above and have it all self-
document.

-- 
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

Tim Wescott <tim@seemywebsite.com> wrote:

(big snip on verilog, VHDL, C, and the differences between them)

> I have to admit, the biggest problem that I have as a C++ programmer when 
> writing in either VHDL or Verilog is envy: in both (IIRC) VHDL or Verilog, 
> when you have a module with a bazzilion input and output signals, you can 
> invoke it with a syntax something like
 
> module_name(module_signal_name = local_signal_name, ...)
 
> In C++, when, for reasons of utility, you are forced to design a class 
> whose constructor has a bazzilion inputs, you have to hold your breath, 
> close your eyes, cross your fingers, and hope that whoever uses that 
> constructor call gets all the right things in all the right places: I'd 
> Much Rather be able to invoke the syntax above and have it all self-
> document.

Fortran now has the keywork form as an option. Also, optional arguments
so that the called routine can figure out which options are needed.

I do remember once mixing verilog and schematic capture. In that case,
you have to use the keyword form, as there is no ordering to the
ports in the schematic. (I tried to find one, but there isn't one.)

Also, some port names started with digits, which it turns out verilog
allows, though I forget how you write them.

-- glen