Michael Morris (@M65C02A)

Michael has 30+ years of experience in aerospace/defense/commercial electronics. In his career Michael has worked in analog, video, RF, digital electronics and developed software/firmware for embedded processors in Fortran, Pascal, C/C++, Ada, and assembler. Michael has extensive experience with Xilinx FPGAs. As a hobby, Michael enjoys vintage computers and re-implementing classic microcomputers using HDLs and FPGAs.

Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm

Michael Morris ● June 14, 2020●10 comments

Michael Morris presents a practical, FPGA-friendly fixed-point implementation of the Goldschmidt algorithm to compute sqrt and 1/sqrt. The post shows how an msb-indexed Y_est table and an N_adj scaling factor produce a reliable initial inverse-square-root estimate for an FP32B16 format, enabling five-iteration convergence. It also covers fixed-point normalization, multiplier/shift tradeoffs, and why this fits a real-time motion-controller use case.

Use DPLL to Lock Digital Oscillator to 1PPS Signal

Michael Morris ● July 24, 2016●8 comments

Michael Morris demonstrates a practical DPLL that locks a Direct Digital Synthesizer to a GPS 1PPS signal, achieving sub-microsecond alignment and removing reference-oscillator frequency error. The design uses a Phase-Frequency Detector for 0 degree phase lock, a multiplier-free α-filter, and a limiter to prevent saturation, and includes coast and re-lock logic plus a synthesizable Verilog reference core.

Use a Simple Microprogram Controller (MPC) to Speed Development of Complex Microprogrammed State Machines

Michael Morris ● April 18, 2015●2 comments

The article presents a synthesizable Verilog microprogram controller (MPC) modeled on the Fairchild F9408 that simplifies development of complex microprogrammed state machines. It explains desirable MPC features — a loadable program counter for sequential and non-sequential execution, conditional and multi-way branching, and a microsubroutine stack — and then provides a working HDL implementation (F9408A_MPC). The module is parameterized for microprogram address width, supports a 4-level LIFO return stack, 8-way multiway branch via an external selector, pipelined or non-pipelined operation, and registered test inputs for conditional branches. The article includes the full Verilog source and discusses practical uses of the MPC in designs from protocol controllers to a 65C02 microprocessor reimplementation.

Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver

Michael Morris ● March 29, 2015●5 comments

Michael Morris shows how to pack many asynchronous serial receivers into the area of a single UART by treating FPGA LUTs as writable storage and sharing logic. Using a 4-bit channel counter, microprogrammed state machine, and time-multiplexed baud/sample resources, he fits 16 receive channels (12 used for Caller ID) into a Spartan II XC2S30 and explains input synchronization, filtering, and the multi-channel FIFO approach.

Use Microprogramming to Save Resources and Increase Functionality

Michael Morris ● March 21, 2015

Microprogramming can rescue an overfull FPGA, Michael Morris shows, by compressing control logic and time-multiplexing FIFO storage. He replaces an ABEL state machine with a small microprogram ROM that uses block RAM for deep Rx/Tx FIFOs and LUT RAM for pointers and counters, freeing about 25 percent of the device. The article includes Verilog comparisons, resource tables, and a microassembler link to reproduce the approach.

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