Use DPLL to Lock Digital Oscillator to 1PPS Signal
Michael Morris demonstrates a practical DPLL that locks a Direct Digital Synthesizer to a GPS 1PPS signal, achieving sub-microsecond alignment and removing reference-oscillator frequency error. The design uses a Phase-Frequency Detector for 0 degree phase lock, a multiplier-free α-filter, and a limiter to prevent saturation, and includes coast and re-lock logic plus a synthesizable Verilog reference core.
Summer of gateware is coming (again)
Wondering what gateware will come out of this summer? Christopher Felton announces MyHDL is back in Google Summer of Code and has been awarded six student slots. Projects span GEMAC, a Leros tiny processor, JPEG encoder front/backends, RISC-V tooling and HDMI+RISC-V work. Follow along for short project updates and a final summer summary.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
Homebrew CPUs: Color Languages
Victor Yurkovsky proposes turning color from mere syntax highlighting into a semantic tool for a Forth-like CPU, letting color pick which stack an operation touches. He outlines a "Rainbow Forth" where green and blue select two datastacks, red denotes the return stack, gray means use the caller's color, and white is neutral. The post sketches CPU changes, a COLOR register, call encoding and immediate-mode coloring, and teases editor and compiler implications for implementing this idea on a J1-style core.
Homebrew CPUs: Messing around with a J1
Victor Yurkovsky takes James Bowman's compact J1 stack CPU and starts hacking: he trims the ALU, replaces the barrel shifter with simpler shifts, and experiments with dual stacks and memory/IO feeding directly into the ALU. The article walks through small, practical changes that cut logic, add instructions, and boost timing on Spartan-6. It's a hands-on tour that shows how approachable homebrew CPUs can be.
Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
Michael Morris shows how to pack many asynchronous serial receivers into the area of a single UART by treating FPGA LUTs as writable storage and sharing logic. Using a 4-bit channel counter, microprogrammed state machine, and time-multiplexed baud/sample resources, he fits 16 receive channels (12 used for Caller ID) into a Spartan II XC2S30 and explains input synchronization, filtering, and the multi-channel FIFO approach.
Use Microprogramming to Save Resources and Increase Functionality
Microprogramming can rescue an overfull FPGA, Michael Morris shows, by compressing control logic and time-multiplexing FIFO storage. He replaces an ABEL state machine with a small microprogram ROM that uses block RAM for deep Rx/Tx FIFOs and LUT RAM for pointers and counters, freeing about 25 percent of the device. The article includes Verilog comparisons, resource tables, and a microassembler link to reproduce the approach.
Yet another PWM
The provided record for Anton Babushkin’s post “Yet another PWM” contains no article body, so the actual technical content is not available for review. The title and site context indicate the post concerns pulse-width modulation (PWM), but specific implementation details, language, or examples cannot be confirmed from the supplied input. This metadata therefore documents the absence of content, recommends steps to recover the original post, and flags that any downstream use (tagging, excerpts, or code extraction) must wait until the full text is retrieved from FPGARelated’s archive or the author’s copy to avoid misrepresentation.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
Use DPLL to Lock Digital Oscillator to 1PPS Signal
Michael Morris demonstrates a practical DPLL that locks a Direct Digital Synthesizer to a GPS 1PPS signal, achieving sub-microsecond alignment and removing reference-oscillator frequency error. The design uses a Phase-Frequency Detector for 0 degree phase lock, a multiplier-free α-filter, and a limiter to prevent saturation, and includes coast and re-lock logic plus a synthesizable Verilog reference core.
Homebrew CPUs: Messing around with a J1
Victor Yurkovsky takes James Bowman's compact J1 stack CPU and starts hacking: he trims the ALU, replaces the barrel shifter with simpler shifts, and experiments with dual stacks and memory/IO feeding directly into the ALU. The article walks through small, practical changes that cut logic, add instructions, and boost timing on Spartan-6. It's a hands-on tour that shows how approachable homebrew CPUs can be.
Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
Michael Morris shows how to pack many asynchronous serial receivers into the area of a single UART by treating FPGA LUTs as writable storage and sharing logic. Using a 4-bit channel counter, microprogrammed state machine, and time-multiplexed baud/sample resources, he fits 16 receive channels (12 used for Caller ID) into a Spartan II XC2S30 and explains input synchronization, filtering, and the multi-channel FIFO approach.
Use Microprogramming to Save Resources and Increase Functionality
Microprogramming can rescue an overfull FPGA, Michael Morris shows, by compressing control logic and time-multiplexing FIFO storage. He replaces an ABEL state machine with a small microprogram ROM that uses block RAM for deep Rx/Tx FIFOs and LUT RAM for pointers and counters, freeing about 25 percent of the device. The article includes Verilog comparisons, resource tables, and a microassembler link to reproduce the approach.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
USB-FPGA : Introduction
Christopher Felton recounts a six-year hobby project to build an open-source USB-FPGA board and its toolchain, from PCB to gateware, firmware, and PC software. He explains why the Cypress FX2 and a Spartan3 were chosen, how the USBP framework supported multiple boards, and why the project’s open-source ambitions didn’t attract the collaboration he expected. Expect practical design and community lessons.
Yet another PWM
The provided record for Anton Babushkin’s post “Yet another PWM” contains no article body, so the actual technical content is not available for review. The title and site context indicate the post concerns pulse-width modulation (PWM), but specific implementation details, language, or examples cannot be confirmed from the supplied input. This metadata therefore documents the absence of content, recommends steps to recover the original post, and flags that any downstream use (tagging, excerpts, or code extraction) must wait until the full text is retrieved from FPGARelated’s archive or the author’s copy to avoid misrepresentation.
Homebrew CPUs: Color Languages
Victor Yurkovsky proposes turning color from mere syntax highlighting into a semantic tool for a Forth-like CPU, letting color pick which stack an operation touches. He outlines a "Rainbow Forth" where green and blue select two datastacks, red denotes the return stack, gray means use the caller's color, and white is neutral. The post sketches CPU changes, a COLOR register, call encoding and immediate-mode coloring, and teases editor and compiler implications for implementing this idea on a J1-style core.
Summer of gateware is coming (again)
Wondering what gateware will come out of this summer? Christopher Felton announces MyHDL is back in Google Summer of Code and has been awarded six student slots. Projects span GEMAC, a Leros tiny processor, JPEG encoder front/backends, RISC-V tooling and HDMI+RISC-V work. Follow along for short project updates and a final summer summary.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
Use DPLL to Lock Digital Oscillator to 1PPS Signal
Michael Morris demonstrates a practical DPLL that locks a Direct Digital Synthesizer to a GPS 1PPS signal, achieving sub-microsecond alignment and removing reference-oscillator frequency error. The design uses a Phase-Frequency Detector for 0 degree phase lock, a multiplier-free α-filter, and a limiter to prevent saturation, and includes coast and re-lock logic plus a synthesizable Verilog reference core.
Homebrew CPUs: Messing around with a J1
Victor Yurkovsky takes James Bowman's compact J1 stack CPU and starts hacking: he trims the ALU, replaces the barrel shifter with simpler shifts, and experiments with dual stacks and memory/IO feeding directly into the ALU. The article walks through small, practical changes that cut logic, add instructions, and boost timing on Spartan-6. It's a hands-on tour that shows how approachable homebrew CPUs can be.
Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
Michael Morris shows how to pack many asynchronous serial receivers into the area of a single UART by treating FPGA LUTs as writable storage and sharing logic. Using a 4-bit channel counter, microprogrammed state machine, and time-multiplexed baud/sample resources, he fits 16 receive channels (12 used for Caller ID) into a Spartan II XC2S30 and explains input synchronization, filtering, and the multi-channel FIFO approach.
Use Microprogramming to Save Resources and Increase Functionality
Microprogramming can rescue an overfull FPGA, Michael Morris shows, by compressing control logic and time-multiplexing FIFO storage. He replaces an ABEL state machine with a small microprogram ROM that uses block RAM for deep Rx/Tx FIFOs and LUT RAM for pointers and counters, freeing about 25 percent of the device. The article includes Verilog comparisons, resource tables, and a microassembler link to reproduce the approach.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
USB-FPGA : Introduction
Christopher Felton recounts a six-year hobby project to build an open-source USB-FPGA board and its toolchain, from PCB to gateware, firmware, and PC software. He explains why the Cypress FX2 and a Spartan3 were chosen, how the USBP framework supported multiple boards, and why the project’s open-source ambitions didn’t attract the collaboration he expected. Expect practical design and community lessons.
Yet another PWM
The provided record for Anton Babushkin’s post “Yet another PWM” contains no article body, so the actual technical content is not available for review. The title and site context indicate the post concerns pulse-width modulation (PWM), but specific implementation details, language, or examples cannot be confirmed from the supplied input. This metadata therefore documents the absence of content, recommends steps to recover the original post, and flags that any downstream use (tagging, excerpts, or code extraction) must wait until the full text is retrieved from FPGARelated’s archive or the author’s copy to avoid misrepresentation.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
Homebrew CPUs: Color Languages
Victor Yurkovsky proposes turning color from mere syntax highlighting into a semantic tool for a Forth-like CPU, letting color pick which stack an operation touches. He outlines a "Rainbow Forth" where green and blue select two datastacks, red denotes the return stack, gray means use the caller's color, and white is neutral. The post sketches CPU changes, a COLOR register, call encoding and immediate-mode coloring, and teases editor and compiler implications for implementing this idea on a J1-style core.
Summer of gateware is coming (again)
Wondering what gateware will come out of this summer? Christopher Felton announces MyHDL is back in Google Summer of Code and has been awarded six student slots. Projects span GEMAC, a Leros tiny processor, JPEG encoder front/backends, RISC-V tooling and HDMI+RISC-V work. Follow along for short project updates and a final summer summary.
