Use DPLL to Lock Digital Oscillator to 1PPS Signal

Michael Morris July 24, 20162 comments
Introduction

There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency oscillator on the leading edge of the 1PPS signal. In many cases, this will result in adequate performance. However, in situations where simple synchronization does not provide adequate performance, digital phase-lock techniques can be applied to a...


Summer of gateware is coming (again)

Christopher Felton April 29, 20162 comments

How time flies!  I swear my last post was a summary of the 2015 summer of gateware.  This year (2016) MyHDL is participating in the Google summer of code again, for the second year, continuing as a sub-org of the Python Software Foundation organization.

This year, so far, has been amazing and inspiring.  We have had many talented students inquire about the project and contribute to myhdl and


An absolute position encoder VHDL core

Fabien Le Mentec November 11, 2015
Introduction

Let's consider motorized systems controlled by electronics. A closed loop architecture looks like this:

The following components are involved:

  • the motor itself (DC, stepper ...),
  • the controller, in charge of computing position according to the whole system state,
  • the driver board in charge of generating signals and power for the motor,
  • the position encoder, the subject of this post.

Most of the time, there is a difference between the position the system...


Homebrew CPUs: Color Languages

Victor Yurkovsky June 18, 2015
Color Languages

Here on bizarro we program using -- get this – text!  Our other senses - hearing, touch, smell, are not used at all. Even our visual perception is greatly underutilized - we just use two-dimensional text on a flat display a foot in front of our eyes.

Color is just beginning to be used, although in a lame syntax coloring way only. Granted, it makes it easier to detect stupid syntax errors such as misspelled keywords. Sadly, color carries zero semantic or...


Homebrew CPUs: Messing around with a J1

Victor Yurkovsky May 29, 2015

In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster.  I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.

J1 CPU

My hat is off to James Bowman.  J1 is pretty cool.  It is a stack machine; it executes instructions in one cycle, it is...


Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver

Michael Morris March 30, 20151 comment
Introduction

This article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.

To stay true to the original design, I...


Use Microprogramming to Save Resources and Increase Functionality

Michael Morris March 21, 2015
Introduction

Microprogramming is a design approach that every FPGA designer should have in their bag of tricks. I subscribe to the concept that microprogramming is a structured approach to the design of state machines. This is essentially the view of Maurice Wilkes when he first proposed microprogramming in 1951 as an alternative method for the implementation of the control section of a computer. Wilkes was interested in improving the reliability and reducing time needed to implement...


Grandiose Delusions

Christopher Felton May 3, 2012

Recently on the MyHDL mailing-list there have been discussions about some other immature Python/HDL tools.  In these discussion it was mentioned, how over the years, there has not been a strong set of open-source IP developed using MyHDL.  For those that might be unfamiliar with the term IP (intellectual property) it is a term widely used in digital hardware to refer to reusable hardware components or blocks.

Many design languages have relied on that first big...


State Machine ‘v’ Micro in a FPGA

Paul J Clarke April 23, 2012

Designing a system and considering if to have a FPGA in the first place is something a engineer should always consider. However one thing that people look to do is designing a microcontroller on a FPGA and in this post I want to consider why we would do it at all and what would be the real consideration for doing this.

We first look at what's available in the microcontroller world. We have a vast range from tiny 8bit 6 pin devices right the way up to monster 32bit devices. These...


Homebrew CPUs: Messing around with a J1

Victor Yurkovsky May 29, 2015

In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster.  I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.

J1 CPU

My hat is off to James Bowman.  J1 is pretty cool.  It is a stack machine; it executes instructions in one cycle, it is...


Use DPLL to Lock Digital Oscillator to 1PPS Signal

Michael Morris July 24, 20162 comments
Introduction

There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency oscillator on the leading edge of the 1PPS signal. In many cases, this will result in adequate performance. However, in situations where simple synchronization does not provide adequate performance, digital phase-lock techniques can be applied to a...


Use Microprogramming to Save Resources and Increase Functionality

Michael Morris March 21, 2015
Introduction

Microprogramming is a design approach that every FPGA designer should have in their bag of tricks. I subscribe to the concept that microprogramming is a structured approach to the design of state machines. This is essentially the view of Maurice Wilkes when he first proposed microprogramming in 1951 as an alternative method for the implementation of the control section of a computer. Wilkes was interested in improving the reliability and reducing time needed to implement...


USB-FPGA : Introduction

Christopher Felton January 12, 20111 comment

This blog is an introduction to a series of blogs I hope to write.  The blogs will cover the design and experiences I had on a project that spanned the last 6 years.  The project was the development of an USB FPGA board and the supporting gateware, firmware, and software.  The project has had different levels of activity over the years, ranging from none to some, but it has been an ongoing project, albeit, during sleepless nights.  Lately, I have ported the HDL (gateware)...


Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver

Michael Morris March 30, 20151 comment
Introduction

This article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.

To stay true to the original design, I...


State Machine ‘v’ Micro in a FPGA

Paul J Clarke April 23, 2012

Designing a system and considering if to have a FPGA in the first place is something a engineer should always consider. However one thing that people look to do is designing a microcontroller on a FPGA and in this post I want to consider why we would do it at all and what would be the real consideration for doing this.

We first look at what's available in the microcontroller world. We have a vast range from tiny 8bit 6 pin devices right the way up to monster 32bit devices. These...


An absolute position encoder VHDL core

Fabien Le Mentec November 11, 2015
Introduction

Let's consider motorized systems controlled by electronics. A closed loop architecture looks like this:

The following components are involved:

  • the motor itself (DC, stepper ...),
  • the controller, in charge of computing position according to the whole system state,
  • the driver board in charge of generating signals and power for the motor,
  • the position encoder, the subject of this post.

Most of the time, there is a difference between the position the system...


Grandiose Delusions

Christopher Felton May 3, 2012

Recently on the MyHDL mailing-list there have been discussions about some other immature Python/HDL tools.  In these discussion it was mentioned, how over the years, there has not been a strong set of open-source IP developed using MyHDL.  For those that might be unfamiliar with the term IP (intellectual property) it is a term widely used in digital hardware to refer to reusable hardware components or blocks.

Many design languages have relied on that first big...


Summer of gateware is coming (again)

Christopher Felton April 29, 20162 comments

How time flies!  I swear my last post was a summary of the 2015 summer of gateware.  This year (2016) MyHDL is participating in the Google summer of code again, for the second year, continuing as a sub-org of the Python Software Foundation organization.

This year, so far, has been amazing and inspiring.  We have had many talented students inquire about the project and contribute to myhdl and