Use DPLL to Lock Digital Oscillator to 1PPS Signal
Michael Morris demonstrates a practical DPLL that locks a Direct Digital Synthesizer to a GPS 1PPS signal, achieving sub-microsecond alignment and removing reference-oscillator frequency error. The design uses a Phase-Frequency Detector for 0 degree phase lock, a multiplier-free α-filter, and a limiter to prevent saturation, and includes coast and re-lock logic plus a synthesizable Verilog reference core.
Point of View
Christopher defends a straightforward MyHDL RTL description of a FIR filter, arguing it is explicit, readable, and concise. He compares that style to a functional hardware description built with Python primitives and list comprehensions, and finds both convert to identical synthesis resources for this example. The post highlights readability tradeoffs and suggests choice often comes down to background and preference.
Little to no benefit from C based HLS
Christopher shows why C-based HLS delivers little practical benefit compared with a MyHDL RTL approach, using a Vivado HLS median-filter example. He walks through the sort-network median, compares C and MyHDL implementations, and argues MyHDL is as concise while providing clearer microarchitecture control. The post emphasizes that choosing the right algorithm is the hard part, and HLS won’t replace hardware understanding.
Shared-multiplier polyphase FIR filter
One multiplier and a dual-port RAM can implement an arbitrary m/n polyphase FIR resampler on an FPGA, Markus Nentwig demonstrates. The post focuses on practical implementation details, including a parametrized Verilog design, pipelined MAC control, and a Matlab testbench for verification. It shows how bank indexing and pipeline delay compensation let you multiplex many coefficient banks efficiently for resource-constrained FPGA designs.
MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
FPGA or DSP Processor - Parameters to Make the Right Choice
Muhammad Yasir breaks down the practical tradeoffs between FPGAs and DSP processors for real-world signal-processing systems. He offers concrete rules of thumb on sampling-rate and data-rate limits, MMAC performance bands, and when conditional logic or floating-point favors a DSP. The post also covers power, form factor, maintainability, and development-time tradeoffs to help architects pick the right platform.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Use DPLL to Lock Digital Oscillator to 1PPS Signal
Michael Morris demonstrates a practical DPLL that locks a Direct Digital Synthesizer to a GPS 1PPS signal, achieving sub-microsecond alignment and removing reference-oscillator frequency error. The design uses a Phase-Frequency Detector for 0 degree phase lock, a multiplier-free α-filter, and a limiter to prevent saturation, and includes coast and re-lock logic plus a synthesizable Verilog reference core.
Shared-multiplier polyphase FIR filter
One multiplier and a dual-port RAM can implement an arbitrary m/n polyphase FIR resampler on an FPGA, Markus Nentwig demonstrates. The post focuses on practical implementation details, including a parametrized Verilog design, pipelined MAC control, and a Matlab testbench for verification. It shows how bank indexing and pipeline delay compensation let you multiplex many coefficient banks efficiently for resource-constrained FPGA designs.
FPGA or DSP Processor - Parameters to Make the Right Choice
Muhammad Yasir breaks down the practical tradeoffs between FPGAs and DSP processors for real-world signal-processing systems. He offers concrete rules of thumb on sampling-rate and data-rate limits, MMAC performance bands, and when conditional logic or floating-point favors a DSP. The post also covers power, form factor, maintainability, and development-time tradeoffs to help architects pick the right platform.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Little to no benefit from C based HLS
Christopher shows why C-based HLS delivers little practical benefit compared with a MyHDL RTL approach, using a Vivado HLS median-filter example. He walks through the sort-network median, compares C and MyHDL implementations, and argues MyHDL is as concise while providing clearer microarchitecture control. The post emphasizes that choosing the right algorithm is the hard part, and HLS won’t replace hardware understanding.
MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
Point of View
Christopher defends a straightforward MyHDL RTL description of a FIR filter, arguing it is explicit, readable, and concise. He compares that style to a functional hardware description built with Python primitives and list comprehensions, and finds both convert to identical synthesis resources for this example. The post highlights readability tradeoffs and suggests choice often comes down to background and preference.
Use DPLL to Lock Digital Oscillator to 1PPS Signal
Michael Morris demonstrates a practical DPLL that locks a Direct Digital Synthesizer to a GPS 1PPS signal, achieving sub-microsecond alignment and removing reference-oscillator frequency error. The design uses a Phase-Frequency Detector for 0 degree phase lock, a multiplier-free α-filter, and a limiter to prevent saturation, and includes coast and re-lock logic plus a synthesizable Verilog reference core.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Shared-multiplier polyphase FIR filter
One multiplier and a dual-port RAM can implement an arbitrary m/n polyphase FIR resampler on an FPGA, Markus Nentwig demonstrates. The post focuses on practical implementation details, including a parametrized Verilog design, pipelined MAC control, and a Matlab testbench for verification. It shows how bank indexing and pipeline delay compensation let you multiplex many coefficient banks efficiently for resource-constrained FPGA designs.
Little to no benefit from C based HLS
Christopher shows why C-based HLS delivers little practical benefit compared with a MyHDL RTL approach, using a Vivado HLS median-filter example. He walks through the sort-network median, compares C and MyHDL implementations, and argues MyHDL is as concise while providing clearer microarchitecture control. The post emphasizes that choosing the right algorithm is the hard part, and HLS won’t replace hardware understanding.
MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
FPGA or DSP Processor - Parameters to Make the Right Choice
Muhammad Yasir breaks down the practical tradeoffs between FPGAs and DSP processors for real-world signal-processing systems. He offers concrete rules of thumb on sampling-rate and data-rate limits, MMAC performance bands, and when conditional logic or floating-point favors a DSP. The post also covers power, form factor, maintainability, and development-time tradeoffs to help architects pick the right platform.
Point of View
Christopher defends a straightforward MyHDL RTL description of a FIR filter, arguing it is explicit, readable, and concise. He compares that style to a functional hardware description built with Python primitives and list comprehensions, and finds both convert to identical synthesis resources for this example. The post highlights readability tradeoffs and suggests choice often comes down to background and preference.
