Professor in the National Technical University of Ukraine -KPI. Deal with FPGA since 1998. My scientific site is My Researchgate profile is

Re: Will this FPGA be suitable for DSP purposes?

Reply posted 3 weeks ago (09/29/2020)
90 DSP48 units of this FPGA are enough to implement a lot of DSP algorithms.But you would rather implement the filters and FFT in the sequential-parallel manner.When...

Re: Processing Gain at output of ADC

Reply posted 5 months ago (06/05/2020)
Really, gain is 5 bits. But in conditions when the signal has not the DC component. If you needn't such a gain you can truncate the resulting bit width to the desired...

Re: How to make sure clock is from the main clock tree?

Reply posted 5 months ago (05/08/2020)
The synthesis tool usually doesn't need the clock frequency at all. But one of the synthesis result is the maximum frequency which provides this design. It is estimated...

Re: How to make sure clock is from the main clock tree?

Reply posted 5 months ago (05/07/2020)
The RTL design paradigm insists that any device must have a clock signal wire and all registers are feeded by it writing the information by the clock edge.So, any...

Re: Suggest a FPGA project

Reply posted 2 years ago (01/07/2019)
Video stream compressor.At present, many old compression method patents are expired,and these methods may be freely implemented in FPGA.Consider GIF.

Re: Pink noise generator on FPGA

Reply posted 2 years ago (12/07/2018)
Usually, the pink noise is derived from the white noise by the filtering.Build the white noise generator based on LSFR, and attach to its output some band pass...

Re: A Law compression for FPGA

Reply posted 2 years ago (08/23/2018)
A-law is an algorithm of the log compression of the audio signals.It attracts for its simplicity. But it works bad for other data compression.You need other kind...

Re: Reduce Phase of a filtered data set

Reply posted 3 years ago (08/16/2017)
There is a special kind of filters called the minimum phase filters.They have unlinear phase characteristic but their group delay is minimized. For example, if a...

Re: Overloading assignment operator '<=' in vhdl

Reply posted 3 years ago (05/15/2017)
the operator '<=' is overloaded for any type of the signal.But the left and right sides must be of the equal type or be subtype of this type.You can assign the...

Re: DSP Filter Verification in FPGA

Reply posted 3 years ago (05/05/2017)
The up conversion filter is calculating the input sequence, which is split by zeros. Therefore, the output results are divided by 2 if the conversion is made up...

Re: manipulation of two dimensional matrices in VHDL

Reply posted 4 years ago (10/13/2016)
In such a situation, I usually use something like perl script to generate the vhdl text with the matrix content. (Perl can be built in the simulator). But in modelling,...

Re: Glitch on Articx7

Reply posted 4 years ago (10/07/2016)
A "glitch" is a product of a bad design. Therefore, it would not be afforded during "translate, map and place and route ". If a real glitch is buried in the...

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