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How to make sure clock is from the main clock tree?

Started by andy92806 1 year ago6 replieslatest reply 1 year ago44 views

Let's say you have a module that needs a clock like this:

module need_clk(i_clk, .....)

 input i_clk;

. .......

endmodule


At the top level, you then have a statement like this then pass the Clock to i_clk.  

always
  begin
    #5 Clock = 1;
    #5 Clock = 0;
  end

My question is how does the synthesis tool determine where to get the clock from?  Will it be just the output of some flip-flop which definitely not recommend?  Will it come from the main clock tree?

I guess my general question is, how you specify to the synthesis tool to use the clock from the main clock tree?



[ - ]
Reply by rajkeerthy18May 7, 2020

Every clock has a source. The clock input(s) to the FPGA would be used to generate the clock required by the circuit. The synthesis and the tools downstream trace the clock source and relative phase/skew slope etc. to generate the circuit from RTL and place and route and analyse timing and generate the program file. 

[ - ]
Reply by asserMay 7, 2020

The RTL design paradigm insists that any device must have a clock signal wire and all registers are feeded by it writing the information by the clock edge.

So, any chip including FPGA has predefined clock wire(s) which source stays out of the chip or in the chip in the form of specific module.

Therefore, you needn't bother about the clock source because it must be present anyway.

Usually the CAD tool affords the input of the clock constrains, and often proposes to consider the signal named CLOCK, which it usually find in your project automatically. 

[ - ]
Reply by andy92806May 7, 2020

Thank you to your replies.

Let's say the FPGA has an input pin for clock.  You feed in 25MHz to the pin so that the FPGA internal clock tree will get 25MHz.

Now you declare a clock something as below using #5 of delay.  But what if you uses #100 as delay which means the frequency now is not 25MHz.  How does the synthesis tool know which clock frequency to generate?

always
begin
    #5 Clock = 1;
    #5 Clock = 0;
end
[ - ]
Reply by kazMay 13, 2020

You got plenty of replies, I will add these notes:

Your above code drives clock for simulation (testbench). In the device the clock is driven on clock pin which is connected to clock global nets.

If you drive a clock internally (and this is not recommended) then you need to tell tool to connect to global nets.

clock frequency at clock pin is needed by tool to optimise timing closure.

[ - ]
Reply by asserMay 8, 2020

The synthesis tool usually doesn't need the clock frequency at all. But one of the synthesis result is the maximum frequency which provides this design. It is estimated by the critical path delay. 

When you want to optimize this frequency you must take the clock constraint to the synthesizer. Then it will try to minimize the critical path to fit this value. So, you can improve the initial frequency estimation in ca. 1.5 times.

When the inner clock manager unit is used then often its working frequency must be given. Usually it is given in the IP core generator wizard, when such a manager is generated.  

[ - ]
Reply by rnpMay 11, 2020

The clock can come from an external source for example. Take for example the Basys 3 board (1), it has an 100 MHz External clock source on (pin W5). You can declare this clock in your constraint file, so Vivado knows is a clock source. Like below:

set_property PACKAGE_PIN W5 [get_ports clk]
create_clock -period 10.000 [get_ports clk]


Additional clocks can be generated using Tcl script commands, if you have a bigger/more complex design. Or again, using Vivado use the clock wizard to generate additional clocks you might need.

I hope this  helps to answer your question.


Regards,

Rafael.


(1) https://reference.digilentinc.com/_media/basys3:ba...