- Electronics Engineer. - Worked on FPGAs and related tools.

i think i misunderstand the diagram with edges. I suppose the 11th edge is nothing but first edge, so from 10 to 11th edge is equal to high period (1 step/1ns)...
I am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like below:I...
Thank you very much for the detailed explanation!Regards
I believe the clock latency is the total time it takes from the clock source to an end point. Whereas, the propagation delay would simply be the delay between...

Use this form to contact tip_can19

Before you can contact a member of the *Related Sites:

  • You must be logged in (register here)
  • You must confirm you email address