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Tip can19 (@tip_can19)

- Electronics Engineer. - Worked on FPGAs and related tools.

Re: How to understand -edge option if first edge of generated clock is falling edge?

Reply posted 5 years ago (10/29/2018)
i think i misunderstand the diagram with edges. I suppose the 11th edge is nothing but first edge, so from 10 to 11th edge is equal to high period (1 step/1ns)...

How to understand -edge option if first edge of generated clock is falling edge?

New thread started 5 years ago
I am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like below:I...

Re: What would be difference between clock latency and propagation delay?

Reply posted 5 years ago (10/28/2018)
Thank you!

Re: What would be difference between clock latency and propagation delay?

Reply posted 5 years ago (10/28/2018)
Thank you very much for the detailed explanation!Regards

What would be difference between clock latency and propagation delay?

New thread started 6 years ago
I believe the clock latency is the total time it takes from the clock source to an end point. Whereas, the propagation delay would simply be the delay between...

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