I've noticed that literally over night ordinary ( non-SERDES, non-automotive) members of ECP5 family is gone on Lattice's...

I've noticed that literally over night ordinary ( non-SERDES, non-automotive) members of ECP5 family is gone on Lattice's pages. Questions: 1. Is there process advancement comming ( 40nm -> 28 nm or similar) 2. Are we to see iCE50, MachXO4, ECP6 shortly ? 3. How much of this is caused by process advancement (like 28 nm becoming more cost-effective than 40nm for the purpose etc) ? 4. How mu

Hello, I use Mike Fields vhdl code for hdmi processing. from Hamsterwork website. I want to Raspberry PI HDMI output connect to FPGA INPUT. I...

Hello, I use Mike Fields vhdl code for hdmi processing. from Hamsterwork website. I want to Raspberry PI HDMI output connect to FPGA INPUT. I try 720p,1080p, progressive, interlaced and any kind of settings HDMI,DVI, component, RGB but result is nothing. I generate TMDS output from other fpga board and connect to HDMI input from other FPGA board and it works.. but Raspberry Pi don't want . ...

When ATPG errors suppose an ATPG errors with slight probability p p-> 0 now suppose it is used to calculate untestability of a...

When ATPG errors suppose an ATPG errors with slight probability p p-> 0 now suppose it is used to calculate untestability of a fault. Let T be 1 if fault is testable, let T be 0 if fault is untestable. Now, suppose we use an errorneous ATPG be T OR A, where A = and(x1,x2......x_n) where n-> infinity. the average for an untestable fault if n-> infinity = = 0 in

They are relatively new: https://www.efinixinc.com Their Trion program has few notable peculiarities: - unified roruting/LUT tiles. One...

They are relatively new: https://www.efinixinc.com Their Trion program has few notable peculiarities: - unified roruting/LUT tiles. One tile can be used for both roles. - 5 bit BLOCK RAM instaed of traditional 9-bit They claim that this and process innovation (only 7 metalic layers) etc that ahould bringg 4x lower prices. But at least from theri initial offering, as much as it can ...

My holy grail has always been a simple CPU combined with a smallish FPGA. There are a few out there, very few, but none of them are available in...

My holy grail has always been a simple CPU combined with a smallish FPGA. There are a few out there, very few, but none of them are available in appropriate packages and inexpensive. I've found a couple of Chinese startups that seem to have some interesting devices. AGM has the AG6K, a 6k LUT with 250 MHz ARM in a QFP100, pretty much the perfect part. Trouble is I can't tell

Can anyone shed some light on why are XO2/3 chips so expenisive compared to ECP5 ? XO2/3 is supposed to be middle-to-low end of their product...

Can anyone shed some light on why are XO2/3 chips so expenisive compared to ECP5 ? XO2/3 is supposed to be middle-to-low end of their product lines, but simple 6900 LUT XO3 is significantly more expensive than 12kLUT ECP5. What gives ?

I found the part I had been interested in, the AGM AG6K SoC with a 250 MHz = ARM Cortex processor, 6,000 LE FPGA, 128 kB SRAM, 12 bit ADC, all in...

I found the part I had been interested in, the AGM AG6K SoC with a 250 MHz = ARM Cortex processor, 6,000 LE FPGA, 128 kB SRAM, 12 bit ADC, all in a 100 = pin QFP package. Works for many of my apps although these days I'd prefer = an 88 pin QFN I think. Good density and still works with 6/6 mil design ru= les, but it has that thermal pad in the center while makes vias difficult u= nderneath ...

On 13/11/2019 07:47, Rick C wrote: > On Tuesday, November 12, 2019 at 4:10:10 AM UTC-5, Michael Kellett wrote: > > On 12/11/2019 01:09, Brane2...

On 13/11/2019 07:47, Rick C wrote: > On Tuesday, November 12, 2019 at 4:10:10 AM UTC-5, Michael Kellett wrote: > > On 12/11/2019 01:09, Brane2 wrote: > > > You might be interested in gowin's program, especially their LittleBee series. > > > > > > To me, it looks like they've nailed. > > > > > > To me, this is everything that MachXO3 should have been... > > > > > > https://www.gowinsemi.com/en/ > > >

It looks like Lattice has announced a new FPGA product that suits my needs. I've always preferred non-BGA devices because they complicate the PCB...

It looks like Lattice has announced a new FPGA product that suits my needs. I've always preferred non-BGA devices because they complicate the PCB fabrication with the need for fine pitch and very small vias. These devices seem to be aimed at products requiring high security, but the other aspects suit me to a tee. There are two size devices, about 4000 LUTs and about 9000 LUTs

We're planning a new universal boot loader for a family of ST processors. The uP would host the loader in a bit of local flash and read an...

We're planning a new universal boot loader for a family of ST processors. The uP would host the loader in a bit of local flash and read an outboard serial flash to get the specific application code and one or more FPGA configurations. So, how many config bits might there be for a modern mid-range FPGA doing a moderately complex application? I think we could enable compression too. ...