Most of us have implemented small processors for logic operations that don't need to happen at high speed. Simple CPUs can be built into an FPGA...

Most of us have implemented small processors for logic operations that don't need to happen at high speed. Simple CPUs can be built into an FPGA using a very small footprint much like the ALU blocks. There are stack based processors that are very small, smaller than even a few kB of memory. If they were easily programmable in something other than C would anyone be interested?

Respected members, I'm a 3rd-year undergrad, majoring on Electronics & Communication Engineering at IIEST Shibpur, India. I have been...

Respected members, I'm a 3rd-year undergrad, majoring on Electronics & Communication Engineering at IIEST Shibpur, India. I have been experimenting on my Artix-7 Basys-3 board since my 2nd-semester and got very fascinated in the field of digital architecture designing. Since then, I have been involved in a number of projects related to this field. It is my request that if any opportunit...

Here is new definition for keyword "if_2", version 2. It is developed based on many discussions after my first post: " New keyword "if_2" is...

Here is new definition for keyword "if_2", version 2. It is developed based on many discussions after my first post: " New keyword "if_2" is suggested for dealing with 2-write port memory." New keyword "if_2" is used to put m-write and n-read memory module from chip manufactures' toolbox behind HDL language so that with the new keyword "if_2" introduction any m-write and n-read memo

Hi, Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle: 1. p1: process(CLK)...

Hi, Here is a code segment showing 2 methods doing 2 writes to an array with 2 different addresses on the same cycle: 1. p1: process(CLK) is begin if CLK'event and CLK = '1' then if C1 then An_Array(a)

Hi, In my opinion, using a 2-write port memory is a mature technique and its implementation in any chip is never a secret. Hardware designers in...

Hi, In my opinion, using a 2-write port memory is a mature technique and its implementation in any chip is never a secret. Hardware designers in HDL often use 2-write port memory in their applications. To relieve hardware designers from repeatedly writing complex code for a 2-write port memory, I suggest here for full HDL grammar spectrum to introduce a new keyword "if_2" and new "

Research Assistantship (Spring, 2020) at the Graduate School, School of Software, Hallym University, Korea The [Advanced AI-Communication...

Research Assistantship (Spring, 2020) at the Graduate School, School of Software, Hallym University, Korea The [Advanced AI-Communication Lab] and [AI Accelerator Design Lab] of the Hallym University seek to recruit promising PhD and MSc or MSc-PhD research students. * [Advanced AI-Communication Lab] The selected students will conduct research in the AI based wireless commun

Hi folks looking for feedback on PipelineC. Ideas of what to implement next. I will point you to a recent reddit post which ultimately points...

Hi folks looking for feedback on PipelineC. Ideas of what to implement next. I will point you to a recent reddit post which ultimately points to GitHub. https://www.reddit.com/r/FPGA/comments/d0x2p5/serial_8x8_dct_in_pipelinec_lower_resource_usage/ Here is the code to get you interested: // This is the unrolled version of the original dct copy-and-pasted algorit

Hi folks looking for feedback on PipelineC. Ideas of what to implement next. I will point you to a recent reddit post which ultimately points...

Hi folks looking for feedback on PipelineC. Ideas of what to implement next. I will point you to a recent reddit post which ultimately points to GitHub. https://www.reddit.com/r/FPGA/comments/d0x2p5/serial_8x8_dct_in_pipelinec_lower_resource_usage/ Here is the code to get you interested: // This is the unrolled version of the original dct copy-and-pasted algorit

Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Vivado remains unable to successfully divide an amount of time you want to...

Y'all. It's 2019. TIME has been in VHDL since what, 1987? And yet Vivado remains unable to successfully divide an amount of time you want to wait by a clock period to get a compile-time integer. https://www.xilinx.com/support/answers/57964.html is from 2014. Five years. In five years, Xilinx has remained unable to perform simple division. Absolutely embarrassing. -- Rob Gaddi...

Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to convert from Bayer...

Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to convert from Bayer pattern to RGB ?